View MT9V032C12STMH_7771643.PDF datasheet online --- IC-ON-LINE

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. mt9v032: 1/3-inch wide-vga digital image sensor features pdf: 6538045704/source:2194051501 . mt9v022_ds - rev.d 5/11 en 1 ?2005 aptina imaging corporation all rights reserved. 1/3-inch wide-vga cmos digital image sensor mt9v032 data sheet for the latest data sheet revision, refer to aptinas web site: www.aptina.com features ? array format: wide-vga, active 752h x 480v (360,960 pixels) ? global shutter photodiode pixels; simultaneous integration and readout ? monochrome or color: near_ir enhanced performance for use with non-visible nir illumination ? readout modes: progressive or interlaced ? shutter efficiency: >99% ? simple two-wire serial interface ? register lock capability ? window size: user programmable to any smaller format (qvga, cif, qcif, etc.). data rate can be maintained independent of window size ? binning: 2 x 2 and 4 x 4 of the full resolution ? adc: on-chip, 10-bit column-parallel (option to operate in 12-bit to 10-bit companding mode) ? automatic controls: auto exposure control (aec) and auto gain control (agc); variable regional and variable weight aec/agc ? support for four unique seri al control register ids to control multiple imagers on the same bus ? data output formats: ? single sensor mode: 10-bit parallel/stand-alone 8-bit or 10-bit serial lvds ? stereo sensor mode: interspersed 8-bit serial lvds applications ?security ? high dynamic range imaging ? unattended surveillance ? stereo vision ?video as input ?machine vision ?automation table 1: key performance parameters ordering information parameter value optical format 1/3-inch active imager size 4.51mm(h) x 2.88mm(v) 5.35mm diagonal active pixels 752h x 480v pixel size 6.0 m x 6.0 m color filter array monochrome or color rgb bayer pattern shutter type global shutter maximum data rate/ master clock 26.6 mps/26.6 mhz full resolution 752 x 480 frame rate 60 fps (at full resolution) adc resolution 10-bit column-parallel responsivity 4.8 v/lux-sec (550nm) dynamic range >55db linear; >80db ? 100db in hidy mode supply voltage 3.3v + 0.3v ( all supplies) power consumption <320mw at maximum data rate; 100 w standby power operating temperature C30c to +70c packaging 48-pin clcc table 2: available part numbers part number description mt9v032c12stm es 48-pin clcc (mono) mt9v032c12stc es 48-pin clcc (color) mt9v032c12stmd es 48-pin clcc demo kit (mono) MT9V032C12STMH es 48-pin clcc headboard only (mono) mt9v032c12stcd es 48-pin clcc demo kit (color) mt9v032c12stch es 48-pin clcc headboard only (color)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev.d 5/11 en 2 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 pixel array structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 color device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 pixel binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 interlaced readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 automatic black level calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 other limiting factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 output data timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 bus idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 data bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 two-wire serial interface sam ple read and write sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 16-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 8-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 register lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 lock all registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 lock read mode register only (r0x0d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 shadowed registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 simultaneous master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 sequential master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 snapshot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 on-chip biases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 adc voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 v_step voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 chip version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 blanking control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 pixel integration control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 total integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 changes to integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
pdf: 6538045704/source:2194051501 mt9v022_ds - rev.d 5/11 en 3 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor table of contents exposure indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 high dynamic range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 variable adc resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 changes to gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 analog gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 black level calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 row-wise noise correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 automatic gain control and automatic exposu re control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 pixel clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 hard reset of logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 soft reset of logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 standby control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 monitor mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 read mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 column flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 row flip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 pixel binning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 row binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 column binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 line_valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 lvds serial (stand-alone/stereo) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 lvds output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 propagation delays for pixclk and data out signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 propagation delays for frame_valid and line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 test 1: sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 test 2: dark signal nonuniformity (dsnu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 test 3: photo response nonuniformity (prnu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 test 4: dynamic range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 test 5: signal-to-noise ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 two-wire serial bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 temperature reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 appendix a ? serial configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 configuration of sensor for stand-alone seri al output with internal pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 configuration of sensor for stereoscopic se rial output with internal pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 broadcast and individual writes for stereoscopic topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 appendix b ? power-on reset and standby timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 reset, clocks, and standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 standby assertion restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 4 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: 48-pin clcc package pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration (connection) ?parallel output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 7: timing example of pixel data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 8: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9: timing diagram showing a write to r0x09 with the valu e 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10: timing diagram showing a read from r0x09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: timing diagram showing a bytewise write to r0x09 wi th the value 0x0284 . . . . . . . . . . . . . . . . . . . .18 figure 12: timing diagram showing a bytewise read from r0x 09; returned value 0x0284 . . . . . . . . . . . . . . . .18 figure 13: simultaneous master mo de synchronization waveforms #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 14: simultaneous master mo de synchronization waveforms #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 15: sequential master mode synchron ization waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 16: snapshot mode interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 17: snapshot mode frame synchronization waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 18: slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 19: signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 20: latency when changing integrat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 21: sequence of control voltages at the hdr gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 22: sequence of voltages in a piecewise linear pixel resp onse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 23: 12- to 10-bit companding chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 24: latency of analog gain change when agc is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 25: tiled sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 26: black level calibration flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 27: controllable and observable aec/agc registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 28: readout of 6 pixels in normal and column flip output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 29: readout of 6 rows in normal an d row flip output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 30: readout of 8 pixels in normal and row bin output mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 31: readout of 8 pixels in normal and column bin output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 32: spatial illustration of interlaced image readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 33: different line_valid formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 34: serial output format for a 6x2 frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 35: propagation delays for pixclk and data out signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 36: propagation delays for frame_vali d and line_valid signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1 figure 37: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 38: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 39: serial host interface data timing for write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 40: serial host interface data timing for read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 41: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 42: acknowledge signal timing after an 8-bit read from th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 43: typical quantum efficiency?color. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 44: typical quantum efficiency?monoc hrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 45: 48-pin clcc package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 46: stand-alone topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 47: stereoscopic topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 48: two-wire serial interface config uration in stereoscopic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 49: power-up, reset, clock and stan dby sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 50: standby restricted lo cation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
pdf: 6538045704/source:2194051501 mt9v022_ds - rev.d 5/11 en 5 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 5: frame time?long integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 6: slave address modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 7: default register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 8: register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 9: lvds packet format in stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 10: lvds packet format in stereoscopy mode (stereoscopy mode bit asserted) . . . . . . . . . . . . . . . . . . .58 table 11: reserved words in the pixel data stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 12: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 13: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 14: ac electrical characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 15: performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 6 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor general description general description the aptina ? mt9v032is a 1/3-inch wide-vga form at cmos active-pixel digital image sensor with global shutter and high dyna mic range (hdr) operation. the sensor has specifically been designed to support the demanding interior and exterior surveillance imaging needs, which makes this part ideal fo r a wide variety of imaging applications in real-world environments. this wide-vga cmos image sensor features aptina?s breakthrough low-noise cmos imaging technology that achieves ccd image quality (based on sign al-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advan- tages of cmos. the active imaging pixel array is 752h x 480v. it incorporates sophisticated camera func- tions on-chip?such as binning 2 x 2 and 4 x 4, to improve sensitivity when operating in smaller resolutions?as well as windowing, column and row mirroring. it is program- mable through a simple two- wire serial interface. the mt9v032 can be operated in its default mode or be programmed for frame size, exposure, gain setting, and other paramete rs. the default mode outputs a wide-vga- size image at 60 fram es per second (fps). an on-chip analog-to-digital converter (adc) pr ovides 10 bits per pi xel. a 12-bit resolu- tion companded for 10 bits for small signals ca n be alternatively enabled, allowing more accurate digitization for darker areas in the image. in addition to a traditional, parallel logic output the mt9v032 also features a serial low- voltage differential signaling (lvds) output. the sensor can be operated in a stereo- camera, and the sensor, designated as a stereo -master, is able to merge the data from itself and the stereo-slave sensor into one serial lvds stream. figure 1: block diagram parallel video data out serial register i/o control register adcs active-pixel sensor (aps) array 752h x 480v timing and control digital processing analog processing serial video lvds out slave video lvds in (for stereo applications only)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 7 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor general description figure 2: 48-pin clcc package pinout diagram 1 2 3 4 5 6 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 lvdsgnd bypass_clkin_n bypass_clkin_p ser_datain_n ser_datain_p lvdsgnd d gnd v dd d out 5 d out 6 d out 7 d out 8 d out 3 d out 4 vaapix v aa a gnd nc nc v aa a gnd standby reset# s_ctrl_adr1 d out 9 line_valid frame_valid stln_out exposure s data sclk stfrm_out led_out oe rsvd s_ctrl_adr0 vddlvds ser_dataout_n ser_dataout_p shft_clkout_n shft_clkout_p v dd d gnd sysclk pixclk d out 0 d out 1 d out 2 48 47 46 45
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 8 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor pin descriptions pin descriptions table 3: pin descriptions only pins d out 0 through d out 9 may be tri-stated. 48-pin llcc numbers symbol type description note 29 rsvd input connect to d gnd .1 10 ser_datain_n input serial data in for stereoscopy (differential negative). tie to 1k pull-up (to 3.3v) in non-stereoscopy mode. 11 ser_datain_p input serial data in for stereoscopy (differential positive). tie to d gnd in non-stereoscopy mode. 8 bypass_clkin_n input input bypass shift-clk (differential negative). tie to 1k pull-up (to 3.3v) in non-stereoscopy mode. 9 bypass_clkin_p input input bypass shift-clk (differential positive). tie to d gnd in non- stereoscopy mode. 23 exposure input rising edge starts exposure in slave mode. 25 sclk input two-wire serial interface clock. connect to v dd with 1.5k resistor even when no other two-wire serial interface peripheral is attached. 28 oe input d out enable pad, active high. 2 30 s_ctrl_adr0 input two-wire serial interface slave address bit 3. 31 s_ctrl_adr1 input two-wire serial interface slave address bit 5. 32 reset# input asynchronous reset. all registers assume defaults. 33 standby input shut down sensor operation for power saving. 47 sysclk input master clock (26.6 mhz). 24 s data i/o two-wire serial interface data. connect to v dd with 1.5k resistor even when no other two-wire serial interface peripheral is attached. 22 stln_out i/o output in master mode ? start line sync to drive slave chip in- phase; input in slave mode. 26 stfrm_out i/o output in master mode ? start frame sync to drive a slave chip in- phase; input in slave mode. 20 line_valid output asserted when d out data is valid. 21 frame_valid output asserted when d out data is valid. 15 d out 5 output parallel pixel data output 5. 16 d out 6 output parallel pixel data output 6. 17 d out 7 output parallel pixel data output 7. 18 d out 8 output parallel pixel data output 8 19 d out 9 output parallel pixel data output 9. 27 led_out output led strobe output. 41 d out 4 output parallel pixel data output 4. 42 d out 3 output parallel pixel data output 3. 43 d out 2 output parallel pixel data output 2. 44 d out 1 output parallel pixel data output 1. 45 d out 0 output parallel pixel data output 0. 46 pixclk output pixel clock out. d out is valid on rising edge of this clock. 2 shft_clkout_n output output shift clk (differential negative). 3 shft_clkout_p output output shift clk (differential positive). 4 ser_dataout_n output serial data out (differential negative). 5 ser_dataout_p output serial data out (differential positive).
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 9 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor pin descriptions note: 1. pin 29 (rsvd) must be tied to gnd. 2. output enable (oe) tri-states signals d out 0Cd out 9. no other signals are tri-stated with oe. 3. no connect. these pins must be left floating for proper operation. figure 3: typical configuration (connection) ? parallel output mode note: lvds signals are to be left floating. 1, 14 v dd supply digital power 3.3v. 35, 39 v aa supply analog power 3.3v. 40 vaapix supply pixel power 3.3v. 6v dd lvds supply dedicated power for lvds pads. 7, 12 lvdsgnd ground dedicated gnd for lvds pads. 13, 48 d gnd ground digital gnd. 34, 38 a gnd ground analog gnd. 36, 37 nc nc no connect. 3 table 3: pin descriptions (continued) only pins d out 0 through d out 9 may be tri-stated. 48-pin llcc numbers symbol type description note sysclk line_valid frame_valid pixclk d out (9:0) standby exposure rsvd s_ctrl_ adr 0 s_ctrl_adr1 lvdsgnd led_out error s data sclk reset# oe v dd lvds a gnd d gnd v dd v aa vaapix master clock 0.1 f to controller standby from controller or digital gnd two-wire serial interface v dd v aa vaapix to led output 10k 1.5k
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 10 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor pixel data format pixel data format pixel array structure the mt9v032 pixel array is configured as 782 columns by 492 rows, shown in figure 4. the left 26 columns and the top eight rows of pixels are optically black and can be used to monitor the black level. the black row data is used internally for the automatic black level adjustment. however, the middle four black rows can also be read out by setting the sensor to raw data output mode. there are 753 columns by 481 rows of optically active pixels. the active area is surrounded with optically transparent dummy columns and rows to improve image uniformity within the active area. one additional active column and active row are used to allow horizontally and vertically mirrored readout to also start on the same color pixel. figure 4: pixel array description figure 5: pixel color pattern detail (top right corner) (782,492) 2 dummy columns 2 dummy rows 8 dark, 1 light dummy rows (0,0) 26 dark, 1 light dummy columns pixel (2,9) row readout direction b g b g b g g r g r g r g r g r g r g r g r g r g r g r g r b g b g b g b g b g b g b g b g b g column resdout direction
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 11 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor color device limitations color device limitations the color version of the mt9v032 does not support or offers reduced performance for the following functionalities. pixel binning pixel binning is done on immedi ate neighbor pixels only; no facility is provided to skip pixels according to a bayer pattern. therefore, the result of binning combines pixels of different colors. for more information, see ?pixel binning? on page 52. interlaced readout interlaced readout yields one field consisting only of red and green pixels and another consisting only of blue and green pixels. this is due to the bayer pattern of the cfa. automatic black level calibration when the color bit is set (r0x0f[2]=1), the sensor uses green1 pixels black level correc- tion value, which is applied to all colors. to use calibration value based on all dark pixels offset values, the color bit should be cleared. other limiting factors black level correction and row-wise noise correction are applied uniformly to each color. automatic exposure and gain control calculations are made based on all three colors, not just the green luma channel. high dyna mic range does operate; however, aptina strongly recommends limiting use to linear operation if good color fidelity is required.
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 12 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor output data format output data format the mt9v032 image data can be read out in a progressive scan or interlaced scan mode. valid image data is surrounded by horizontal and vertical blanking, as shown in figure 6. the amount of horizontal and vertical bl anking is programmable through r0x05 and r0x06, respectively. line_valid is high during the shaded region of the figure. see ?output data timing? on page 13 for the description of frame_valid timing. figure 6: spatial illustration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 13 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor output data format output data timing the data output of the mt9v032 is sync hronized with the pixclk output. when line_valid is high, one 10-bit pixel datum is output every pixclk period. figure 7: timing example of pixel data the pixclk is a nominally inverted version of the master clock (sysclk). this allows pixclk to be used as a clock to latch the data. however, when column bin 2 is enabled, the pixclk is high for one complete master clock master period and then low for one complete master clock period; when column bin 4 is enabled, the pixclk is high for two complete master clock periods and then low for two complete master clock periods. it is continuously enabled, even during the blanking period. setting r0x74 bit[4] = 1 causes the mt9v032 to invert the polarity of the pixclk. the parameters p1, a, q, and p2 in figure 8 are defined in table 4. figure 8: row timing and frame_valid/line_valid signals table 4: frame time parameter name equation default timing at 26.66 mhz a active data time r0x04 752 pixel clocks = 752 master = 28.20 s p1 frame start blanking r0x05 - 23 71 pixel clocks = 71master = 2.66 s p2 frame end blanking 23 (fixed) 23 pixel clocks = 23 master = 0.86 s q horizontal blanking r0x05 94 pixel clocks = 94 master = 3.52 s line_valid pixclk d out (9:0) p 0 (9:0) p 1 (9:0) p2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) valid image data blanking blanking ... ... ... ... p1 a q a q a p2 number of master clocks frame_valid line_valid ... ... ...
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 14 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor output data format sensor timing is shown above in terms of pi xel clock and master clock cycles (refer to figure 7 on page 13). the recommended master clock frequency is 26.66 mhz. the vertical blanking and total fr ame time equations assume that the number of integration rows (bits 11 through 0 of r0x0b) is less than the number of active rows plus blanking rows minus overhead rows (r0x03 + r0x06 - 2). if this is not the case, the number of inte- gration rows must be used instead to determ ine the frame time, as shown in table 5. in this example it is assumed that r0x0b is programmed with 523 rows. for simultaneous mode, if the exposure time register (0x0b) exceeds the total readout time, then vertical blanking is internally extended automaticall y to adjust for the additional integration exposure time required. this extended value is not written back to r0x06 (vertical blanking). r0x06 can be used to adjust frame to frame readout time. this register does not affect the exposure time but it may extend the readout time. note: 1. the mt9v032 uses column parallel analog-to-digital converters, thus short row timing is not possible. the minimum total row time is 660 columns (horizontal width + horizontal blanking). the minimum horizontal blanking is 43. when the window width is set below 617, horizontal blanking must be increased. the frame rate will not increase for row times less than 660 columns. a+q row time r0x04 + r0x05 846 pixel clocks = 846 master = 31.72 s v vertical blanking (r0x06) x (a + q) + 4 38,074 pixel clocks = 38,074 master = 1.43ms nrows x (a + q) frame valid time (r0x03) (a + q) 406,080 pixel clocks = 406,080 master = 15.23ms f total frame time v + (nrows x (a + q)) 444,154 pixel clocks = 444,154 master = 16.66ms table 5: frame timelong integration time parameter name equation (number of master clock cycles) default timing at 26.66 mhz v vertical blanking (long integration time) (r0x0b + 2 - r0x03) (a + q) + 4 38,074 pixel clocks = 38,074 master = 1.43ms f total frame time (long integration exposure time) (r0x0b + 2) (a + q) + 4 444,154 pixel clocks = 444,154 master = 16.66ms table 4: frame time (continued) parameter name equation default timing at 26.66 mhz
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 15 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor serial bus description serial bus description registers are written to and read from the mt9v032 through the two-wire serial inter- face bus. the mt9v032 is a serial interfac e slave with four possible ids (0x90, 0x98, 0xb0,and 0xb8) determined by the s_ctrl_a dr0 and s_ctrl_adr1 input pins. data is transferred into the mt9v032 and out through the serial data (s data ) line. the s data line is pulled up to v dd off-chip by a 1.5k resistor. either the slave or master device can pull the s data line down?the serial interface pr otocol determines which device is allowed to pull the s data line down at any given time. the registers are 16-bit wide, and can be accessed through 16- or 8-bit two-wire serial interface sequences. protocol the two-wire serial interface defines several different transmission codes, as follows: ?a start bit ? the slave device 8-bit address ? a(n) (no) acknowledge bit ? an 8-bit message ?a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device?s 8-bi t address. the last bit of the address deter- mines if the request is a read or a write, wh ere a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the sl ave sends an acknowledge bit to indicate that the register address has been received. the master then tr ansfers the data 8 bits at a time, with the slave sending an acknowledge bi t after each 8 bits. the mt9v032 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register address is automa tically incremented, so that the next 16 bits are written to the next register address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read mode slave addres s. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented after ever y 16 bits is transferred. the data transfer is stopped when the master sends a no-ack nowledge bit. the mt9v032 allows for 8-bit data transfers through the two-wire serial interface by writing (or reading) the most significant 8 bits to the register and then writ ing (or reading) the least significant 8 bits to r0xf0 (240). bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits.
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 16 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor serial bus description start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of 7 bits of address and 1 bit of direction. a ?0? in the lsb of the ad dress indicates write mode, and a ?1? indicates read mode. as indicated above, the mt9v032 allows four possible slave addresses deter- mined by the two input pins, s_ctrl_adr0 and s_ctrl_adr1. data bit transfer one data bit is transferred during each clock pulse. the two-wire serial interface clock pulse is provided by the master. the data must be stable during the high period of the serial clock?it can only change when the two-wire serial interface clock is low. data is transferred 8 bits at a time, fo llowed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence. table 6: slave address modes {s_ctrl_adr1, s_ctrl_adr0} slave address write/read mode 00 0x90 write 0x91 read 01 0x98 write 0x99 read 10 0xb0 write 0xb1 read 11 0xb8 write 0xb9 read
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 17 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences two-wire serial interface sample read and write sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 9. a start bit given by the master, followed by the write address, starts the sequence. the image sensor then gives an acknowledge bit and expects the re gister address to come first, followed by the 16-bit data. after each 8-bit word is sent, the image sensor gives an acknowledge bit. all 16 bits must be written before the register is updated. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. the master stops writ ing by sending a start or stop bit. figure 9: timing diagram showing a write to r0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 10. first the master has to write the register address, as in a write sequence. then a start bit and the read address specify that a read is about to happen from the register. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented af ter every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 10: timing diagram showing a read from r0x09; returned value 0x0284 sclk s data start ack 0xb8 addr ack ack ack stop r0x09 1000 0100 0000 0010 sclk s data start ack 0xb8 addr 0xb9 addr 0000 0010 r0x09 ack ack ack stop 1000 0100 nack
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 18 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences 8-bit write sequence to be able to write 1 byte at a time to the re gister, a special register address is added. the 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the special register addres s (r0xf0). the register is not updated until all 16 bits have been written. it is not po ssible to just update half of a register. in figure 11 on page 18, a typical sequence for 8-bit writing is shown. the second byte is written to the special register (r0xf0). figure 11: timing diagram showing a bytewise write to r0x09 with the value 0x0284 8-bit read sequence to read one byte at a time the same special register address is used for the lower byte. the upper 8 bits are read from the desired register. by following this with a read from the special register (r0xf1) the lower 8 bits are accessed (figure 12). the master sets the no- acknowledge bits shown. figure 12: timing diagram showing a bytewise read from r0x09; returned value 0x0284 stop r0xf0 ack start 0xb8 addr ack s data sclk ack ack ack ack r0x09 0xb8 addr 0000 0010 1000 0100 start start 0xb9 addr s data sclk stop nack ack ack ack r0x09 start 0xb8 addr 0000 0010 start 0xb9 addr s data sclk nack ack ack ack r0xf0 start 0xb8 addr 1000 0100
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 19 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences register lock included in the mt9v032 is a register lock (r0xfe) feature that can be used as a solution to reduce the probability of an inadverten t noise-triggered two-wire serial interface write to the sensor. all registers (or read mo de register?register 13 only) can be locked. at power-up, the register lock defaults to a value of 0xbeef, which implies that all registers are unlocked and any two-wire seri al interface writes to the register get committed. lock all registers if a unique pattern (0xdead) to r0xfe is programmed, any subseque nt two-wire serial interface writes to registers (except r0xfe) are not committed. alternatively, if the user writes a 0xbeef to the register lock re gister, all registers are unlocked and any subsequent two-wire serial interface writes to the register are committed. lock read mode register only (r0x0d) if a unique pattern (0xdeaf) to r0xfe is programmed, any subsequent two-wire serial interface writes to register 13 are not commi tted. alternatively, if the user writes a 0xbeef to register lock register, register 13 is unlocked and any subsequent two-wire serial interface writes to this register are committed.
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 20 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers registers caution writing and changing the value of a reserved register (word or bit) puts the device in an unknown state and may damage the device. table 7 provides default register descriptions of the registers. table 8 on page 24 provides detailed descriptions of the registers. table 7: default register descriptions 1 = always 1; 0 = always 0; d = programmable; ? = read only register # (hex) description data format (binary) default value (hex) 0x00 chip version 0001 0011 0001 00001 (lsb) iter. 1: 0x1311 iter. 2: 0x1311 iter. 3: 0x1313 0x01 column start 0000 00dd dddd dddd 0x0001 0x02 row start 0000 000d dddd dddd 0x0004 0x03 window height 0000 000d dddd dddd 0x01e0 0x04 window width 0000 00dd dddd dddd 0x02f0 0x05 horizontal blanking 0000 00dd dddd dddd 0x005e 0x06 vertical blanking 0ddd dddd dddd dddd 0x002d 0x07 chip control 0000 dddd dddd dddd 0x0388 0x08 shutter width 1 0ddd dddd dddd dddd 0x01bb 0x09 shutter width 2 0ddd dddd dddd dddd 0x01d9 0x0a shutter width ctrl 0000 00dd dddd dddd 0x0164 0x0b total shutter width 0ddd dddd dddd dddd 0x01e0 0x0c reset 0000 0000 0000 00dd 0x0000 0x0d read mode 0000 0011 dddd dddd 0x0300 0x0e monitor mode 0000 0000 0000 000d 0x0000 0x0f pixel operation mode 0000 0000 dddd dddd 0x0011 0x10 reserved C 0x0040 0x11 reserved C 0x8042 0x12 reserved C 0x0022 0x13 reserved C 0x2d32 0x14 reservedl C 0x0e02 0x15 reserved C 0x7f32 0x16 reserved C 0x2802 0x17 reserved C 0x3e38 0x18 reserved C 0x3e38 0x19 reserved C 0x2802 0x1a reserved C 0x0428 0x1b led_out ctrl 0000 0000 0000 00dd 0x0000 0x1c adc mode control 0000 0000 0000 00dd 0x0002 0x1d reserved C 0x0000 0x1e reserved C 0x0000 0x1f reserved C 0x0000 0x20 reserved C 0x01d1 0x21 reserved C 0x0020 0x22 reserved C 0x0020
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 21 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0x23 reserved C 0x0010 0x24 reserved C 0x0010 0x25 reserved C 0x0020 0x26 reserved C 0x0010 0x27 reserved C 0x0010 0x28 reserved C 0x0010 0x29 reserved C 0x0010 0x2a reserved C 0x0020 0x2b reserved C 0x0004 0x2c v ref _adc control 0000 0000 0000 0ddd 0x0840 0x2d reserved C 0x0004 0x2e reserved C 0x0007 0x2f reserved C 0x0004 0x30 reserved C 0x0003 0x31 v1 0000 0000 000d dddd 0x001d 0x32 v2 0000 0000 000d dddd 0x0018 0x33 v3 0000 0000 000d dddd 0x0015 0x34 v4 0000 0000 000d dddd 0x0004 0x35 analog gain 0000 0000 0ddd dddd 0x0010 0x36 max analog gain 0000 0000 0ddd dddd 0x0040 0x37 reserved C 0x0000 0x38 reserved C 0x0000 0x42 frame dark average 0000 0000 ???? ???? ro 0x46 dark avg thresholds dddd dddd dddd dddd 0x231d 0x47 bl calib control 1000 0000 ddd0 000d 0x8080 0x48 bl calibration value 0000 0000 dddd dddd 0x0000 0x4c bl calib step size 0000 0000 000d dddd 0x0002 0x60 reserved C 0x0000 0x61 reserved C 0x0000 0x62 reserved C 0x0000 0x63 reserved C 0x0000 0x64 reserved C 0x0000 0x65 reserved C 0x0000 0x66 reserved C 0x0000 0x67 reserved C 0x0000 0x68 reserved C ro 0x69 reserved C ro 0x6a reserved C ro 0x6b reserved C ro 0x6c reserved C 0x0000 0x70 row noise corr ctrl 1 0000 d000 00d1 dddd 0x0034 0x71 reserved C 0x0000 0x72 row noise constant 0000 0000 dddd dddd 0x002a 0x73 row noise corr ctrl 2 0000 00dd dddd dddd 0x02f7 0x74 pixclk, fv, lv 0000 0000 000d dddd 0x0000 table 7: default register descriptions (continued) 1 = always 1; 0 = always 0; d = programmable; ? = read only register # (hex) description data format (binary) default value (hex)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 22 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0x7f digital test pattern 0ddd ddd dddd dddd 0x0000 0x80 tile weight/gain x0_y0 0000 0000 dddd dddd 0x00f4 0x81 tile weight/gain x1_y0 0000 0000 dddd dddd 0x00f4 0x82 tile weight/gain x2_y0 0000 0000 dddd dddd 0x00f4 0x83 tile weight/gain x3_y0 0000 0000 dddd dddd 0x00f4 0x84 tile weight/gain x4_y0 0000 0000 dddd dddd 0x00f4 0x85 tile weight/gain x0_y1 0000 0000 dddd dddd 0x00f4 0x86 tile weight/gain x1_y1 0000 0000 dddd dddd 0x00f4 0x87 tile weight/gain x2_y1 0000 0000 dddd dddd 0x00f4 0x88 tile weight/gain x3_y1 0000 0000 dddd dddd 0x00f4 0x89 tile weight/gain x4_y1 0000 0000 dddd dddd 0x00f4 0x8a tile weight/gain x0_y2 0000 0000 dddd dddd 0x00f4 0x8b tile weight/gain x1_y2 0000 0000 dddd dddd 0x00f4 0x8c tile weight/gain x2_y2 0000 0000 dddd dddd 0x00f4 0x8d tile weight/gain x3_y2 0000 0000 dddd dddd 0x00f4 0x8e tile weight/gain x4_y2 0000 0000 dddd dddd 0x00f4 0x8f tile weight/gain x0_y3 0000 0000 dddd dddd 0x00f4 0x90 tile weight/gain x1_y3 0000 0000 dddd dddd 0x00f4 0x91 tile weight/gain x2_y3 0000 0000 dddd dddd 0x00f4 0x92 tile weight/gain x3_y3 0000 0000 dddd dddd 0x00f4 0x93 tile weight/gain x4_y3 0000 0000 dddd dddd 0x00f4 0x94 tile weight/gain x0_y4 0000 0000 dddd dddd 0x00f4 0x95 tile weight/gain x1_y4 0000 0000 dddd dddd 0x00f4 0x96 tile weight/gain x2_y4 0000 0000 dddd dddd 0x00f4 0x97 tile weight/gain x3_y4 0000 0000 dddd dddd 0x00f4 0x98 tile weight/gain x4_y4 0000 0000 dddd dddd 0x00f4 0x99 tile coord. x 0/5 0000 00dd dddd dddd 0x0000 0x9a tile coord. x 1/5 0000 00dd dddd dddd 0x0096 0x9b tile coord. x 2/5 0000 00dd dddd dddd 0x012c 0x9c tile coord. x 3/5 0000 00dd dddd dddd 0x01c2 0x9d tile coord. x 4/5 0000 00dd dddd dddd 0x0258 0x9e tile coord. x 5/5 0000 00dd dddd dddd 0x02f0 0x9f tile coord. y 0/5 0000 000d dddd dddd 0x0000 0xa0 tile coord. y 1/5 0000 000d dddd dddd 0x0060 0xa1 tile coord. y 2/5 0000 000d dddd dddd 0x00c0 0xa2 tile coord. y 3/5 0000 000d dddd dddd 0x0120 0xa3 tile coord. y 4/5 0000 000d dddd dddd 0x0180 0xa4 tile coord. y 5/5 0000 000d dddd dddd 0x01e0 0xa5 aec/agc desired bin 0000 0000 00dd dddd 0x003a 0xa6 aec update frequency 0000 0000 0000 dddd 0x0002 0xa7 reserved C 0x0000 0xa8 aec lpf 0000 0000 0000 00dd 0x0000 0xa9 agc update frequency 0000 0000 0000 dddd 0x0002 0xaa reserved C 0x0000 0xab agc lpf 0000 0000 0000 00dd 0x0002 table 7: default register descriptions (continued) 1 = always 1; 0 = always 0; d = programmable; ? = read only register # (hex) description data format (binary) default value (hex)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 23 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers shadowed registers some sensor settings cannot be changed duri ng frame readout. for example, changing the register window width (r0x04) part way through frame readout results in inconsis- tent line_valid behavior. to avoid this, th e mt9v032 double buffers many registers by implementing a ?pending? and a ?live? vers ion. two-wire serial interface reads and writes access the pending register. the live re gister controls the sensor operation. the value in the pending register is transferred to a live register at a fixed point in the frame timing, called ?frame-start.? frame-start is defined as the point at which the first dark row is read out. by default, this occurs four row times before frame_valid goes high. to determine which registers or register field s are double-buffered in this way, see the ?shadowed? column in table 8. notation used in the register description table: ?shadowed n = no. the register value is updated and used immediately. y = yes. the register value is updated at ne xt frame start. frame start is defined as 0xaf aec/agc enable 0000 0000 0000 00dd 0x0003 0xb0 aec/agc pix count dddd dddd dddd dddd 0xabe0 0xb1 lvds master ctrl 0000 0000 0000 dddd 0x0002 0xb2 lvds shift clk ctrl 0000 0000 000d 0ddd 0x0010 0xb3 lvds data ctrl 0000 0000 000d 0ddd 0x0010 0xb4 data stream latency 0000 0000 0000 00dd 0x0000 0xb5 lvds internal sync 0000 0000 0000 000d 0x0000 0xb6 lvds payload control 0000 0000 0000 000d 0x0000 0xb7 stereoscop. error ctrl 0000 0000 0000 0ddd 0x0000 0xb8 stereoscop. error flag 0000 0000 0000 000? ro 0xb9 lvds data output ???? ???? ???? ???? ro 0xba agc gain output 0000 0000 0??? ???? ro 0xbb aec gain output ???? ???? ???? ???? ro 0xbc agc/aec current bin 0000 0000 00?? ???? ro 0xbd maximum shutter width dddd dddd dddd dddd 0x01e0 0xbe agc/aec bin difference threshold 0000 0000 dddd dddd 0x0014 0xbf field blank 0000 000d dddd dddd 0x0016 0xc0 mon mode capture ctrl 0000 0000 dddd dddd 0x000a 0xc1 temperature 0000 00?? ???? ???? ro 0xc2 analog controls dddd dddd dddd dddd 0x0840 0xc3 ntsc fv & lv ctrl 0000 0000 0000 00dd 0x03840 0xc4 ntsc horiz blank ctrl dddd dddd dddd dddd 0x4416 0xc5 ntsc vert blank ctrl dddd dddd dddd dddd 0x4421 0xf0 bytewise addr C 0x0000 0xf1 reserved C reserved 0xfe register lock dddd dddd dddd dddd 0xbeef 0xff chip version 0001 0011 0000 0000 iter. 1: 0x1311 iter. 2 : 0x1311 iter. 3: 0x1313 table 7: default register descriptions (continued) 1 = always 1; 0 = always 0; d = programmable; ? = read only register # (hex) description data format (binary) default value (hex)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 24 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers when the first dark row is read out. by de fault this is four rows before frame_valid goes high. ?read/write r = read-only register/bit. w = read/write register/bit. table 8 provides a detailed description of the registers. bit fields that are not identified in the table are read only. table 8: register descriptions bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write 0x00/0xff (0/255) chip version 15:0 chip version chip versionread-only iter. 1: 0x1311 (4881) iter. 2: 0x1311 (4881) iter. 3: 0x1313 (4883) r 0x01 (1) column start 9:0 column start the first column to be read out (not counting dark columns that may be read). to window the image down, set this register to the starting x value. readable/ active columns are 1C752. 1 y 1C752 w 0x02 (2) row start 8:0 row start the first row to be read out (not counting any dark rows that may be read). to window the image down, set this register to the starting y value. setting a value less than four is not recommended since the dark rows should be read using r0x0d. 4 y 4C482 w 0x03 (3) window height 8:0 window height number of rows in the image to be read out (not counting any dark rows or border rows that may be read). 1e0 (480) y 1C480 w 0x04 (4) window width 9:0 window width number of columns in image to be read out (not counting any dark columns or border columns that may be read). 2f0 (752) y 1C752 w 0x05 (5) horizontal blanking 9:0 horizontal blanking number of blank columns in a row. minimum horizontal blanking is 43 columns. 05e (94) y 43C1023 w 0x06 (6) vertical blanking 14:0 vertical blanking number of blank rows in a frame. this number must be equal to or larger than four. 002d (45) y 4C3000 w
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 25 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0x07 (7) chip control 2:0 scan mode 0 = progressive scan. 1 = not valid. 2 = two-field interlaced scan. even-numbered rows are read first, and followed by odd-numbered rows. 3 = single-field interlaced scan. if start address is even number, only even-numbered rows are read out; if start address is odd number, only odd-numbered rows are read out. effective image size is decreased by half. 0 y 0, 2, 3 w 3sensor master/ slave mode 0 = slave mode. initiating exposure and readout is allowed. 1 = master mode. sensor generates its own exposure and readout timing according to simultaneous/ sequential mode control bit. 1y0,1w 4 sensor snapshot mode 0 = snapshot disabled. 1 = snapshot mode enabled. the start of frame is triggered by providing a pulse at exposure pin. sensor master/slave mode should be set to logic 1 to turn on this mode. 0y0,1w 5 stereoscopy mode 0 = stereoscopy disabled. sensor is stand-alone and the pll generates a 320 mhz (x12) clock. 1 = stereoscopy enabled. the pll generates a 480 mhz (x18) clock. 0y0,1w 6 stereoscopic master/slave mode 0 = stereoscopic master. 1 = stereoscopic slave. stereoscopy mode should be enabled when using this bit. 0y0,1w 7 parallel output enable 0 = disable parallel output. d out (9:0) are in high-z. 1= enable parallel output. 1y0,1w 8 simultaneous/ sequential mode 0 = sequential mode. pixel and column readout takes place only after exposure is complete. 1 = simultaneous mode. pixel and column readout takes place in conjunction with exposure. 1y0,1w 0x08 (8) shutter width 1 14:0 shutter width 1 the row number in which the first knee occurs. this may be used only when high dynamic range option (bit 6 of r0x0f) is enabled and exposure knee point auto adjust control bit is disabled. this register is not shadowed, but any change made does not take effect until the following new frame. 1bb (443) n 1C32767 w 0x09 (9) shutter width 2 14:0 shutter width 2 the row number in which the second knee occurs. this may be used only when high dynamic range option (bit 6 of r0x0f) is enabled and exposure knee point auto adjust control bit is disabled. this register is not shadowed, but any change made does not take effect until the following new frame. shutter width 2 = (bits 14:0) note: t 1 = shutter width 1; t 2 = shutter width 2 C shutter 1; t 3 = total integration C shutter width 2. 1d9 (473) n 1C32767 w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 26 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0x0a (10) shutter width control 3:0 t2 ratio one-half to the power of this value indicates the ratio of duration time t 2 , when saturation control gate is adjusted to level v2 to total integration when exposure knee point auto adjust control bit is enabled. this register is not shadowed, but any change made does not take effect until the following new frame. t 2 = total integration (?) t2_ratio . 4 n 0C15 w 7:4 t3 ratio one-half to the power of this value indicates the ratio of duration time t 3 , when saturation control gate is adjusted to level v3 to total integration when exposure knee point auto adjust control bit is enabled. this register is not shadowed, but any change made does not take effect until the following new frame. t 3 = total integration (?) t3_ratio . note: t 1 = total integration - t 2 - t 3 . 6 n 0C15 w 8 exposure knee point auto adjust enable 0 = auto adjust disabled. 1 = auto adjust enabled. 1n0,1w 9 single knee enable 0 = single knee disabled. 1 = single knee enabled. 0n0,1w 0x0b (11) total shutter width 14:0 total shutter width total integration time in number of rows. this value is used only when aec is disabled only (bit 0 of register 175). this register is not shadowed, but any change made does not take effect until the following new frame. 1e0 (480) n 1C32767 w 0x0c (12) reset 0 soft reset setting this bit causes the sensor to abandon the current frame by resetting all digital logic except two- wire serial interface configuration. this is a self- resetting register bit and should always read 0. (this bit de-asserts internal active low reset signal for 15 clock cycles.) 0n0, 1w 1auto block soft reset setting this bit causes the sensor to reset the automatic gain and exposure control logic. this is a self-resetting register bit and should always read 0. (this bit de- asserts internal active low reset signal for 15 clock cycles.) 0y0, 1w 0x0d (13) read mode 1:0 row bin 0 = normal operation. 1 = row bin 2. two pixel rows are read per row output. image size is effectively reduced by a factor of 2 vertically while data rate and pixel clock are not affected. resulting frame rate is increased by 2. 2 = row bin 4. four pixel rows are read per row output. image size is effectively reduced by a factor of 4 vertically while data rate and pixel clock are not affected. resulting frame rate is increased by 4. 3 = not valid. 0 y 0, 1, 2 w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 27 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 3:2 column bin 0 = normal operation. 1 = column bin 2. when set, image size is reduced by a factor of 2 horizontally. frame rate is not affected but data rate and pixel clock are reduced by one-half that of master clock. 2 = column bin 4. when set, image size is reduced by a factor of 4 horizontally. frame rate is not affected but data rate and pixel clock are reduced by one-fourth that of master clock. 3 = not valid. 0 y 0, 1, 2 w 4 row flip read out rows from bottom to top (upside down). when set, row readout starts from row (row start + window height) and continues down to (row start + 1). when clear, readout starts at row start and continues to (row start + window height - 1). this ensures that the starting color is maintained. 0y0, 1w 5 column flip read out columns from right to left (mirrored). when set, column readout starts from column (col start + window width) and continues down to (col start + 1). when clear, readout starts at col start and continues to (col start + window width - 1). this ensures that the starting color is maintained. 0y0, 1w 6 show dark rows when set, the programmed dark rows is output before the active window. frame valid is thus asserted earlier than normal. this has no effect on integration time or frame rate. whether the dark rows are shown in the image or not the definition frame start is before the dark rows are read out. 0y0, 1w 7show dark columns when set, the programmed dark columns are output before the active pixels in a line. line valid is thus asserted earlier than normal, and the horizontal blank time gets shorter by 18 pixel clocks. 0y0, 1w 9:8 reserved reserved. 3 0x0e (14) monitor mode 0 monitor mode enable setting this bit puts the sensor into a cycle of sleeping for five minutes, and waking up to capture a programmable number of frames (r0xc0). clearing this bit resumes normal operation. 0y0, 1w 0x0f (15) pixel operation mode 2 color/mono should be set according to sensor type: 0 = monochrome. 1 = color. 0y0, 1w 6 high dynamic range 0 = linear operation. 1 = high dynamic range. voltage and shutter width must be correctly set for saturation control to operate. 0y0, 1w 0x1b (27) led_out control 0 disable led_out disable led_out output. when cleared, the output pin led_out is pulsed high when the sensor is undergoing exposure. 0y0, 1w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 28 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 1 invert led_out invert polarity of led_out output. when set, the output pin led_out is pulsed low when the sensor is undergoing exposure. 0y0, 1w 0x1c (28) adc resolution control 1:0 adc mode 0 = invalid. 1 = invalid. 2 = 10-bit linear. 3 = 12-to10-bit companding. 2y2, 3w 0x2c (44) v ref _adc control 2:0 v ref _adc voltage level 0 = v ref _adc = 1.0v. 1 = v ref _adc = 1.1v. 2 = v ref _adc = 1.2v. 3 = v ref _adc = 1.3v. 4 = v ref _adc = 1.4v. 5 = v ref _adc = 1.5v. 6 = v ref _adc = 1.6v. 7 = v ref _adc = 2.1v. range: 1.0C2.1v; default: 1.4v v ref _adc for adc. 4 n 0C7 w 0x31 (49) v1 control 4:0 v1 voltage level v_step = bits (4:0) x 62.5mv + 0.5625v. range: 0.5625 - 2.5v; default: 2.375v. usage: v_step1 hidy voltage. 1d (29) n 0C31 w 0x32 (50) v2 control 4:0 v2 voltage level v_step = bits (4:0) x 62.5mv + 0.5625v. range: 0.5625 - 2.5v; default: 2.0625v. usage: v_step2 hidy voltage. 18 (24) n 0C31 w 0x33 (51) v3 control 4:0 v3 voltage level v_step = bits (4:0) x 62.5mv + 0.5625v. range: 0.5625 - 2.5v; default: 1.875v. usage: v_step3 hidy voltage. 15 (21) n 0C31 w 0x34 (52) v4 control 4:0 v4 voltage level v_step = bits (4:0) x 62.5mv + 0.5625v. range: 0.5625 - 2.5v; default: 0.8125v. usage: v_step hidy parking voltage, also provides anti- blooming when v_step is disabled. 4 n 0C31 w 0x35 (53) analog gain 6:0 analog gain analog gain = bits (6:0) x 0.0625 for values 16C31: analog gain = bits (6:0)/2 x 0.125 for values 32C64 for values 16C31: each lsb increases analog gain 0.0625v/v. a value of 16 = 1x gain. range: 1x to 1.9375x. for values 32C64: each 2 lsb increases analog gain 0.125v/v. range: 2x to 4x. an lsb increase of 1 w ill not increase the gain; the value must be incremented by 2. no exception detection is installed and caution should be taken when programming. 10 (16) y 16C64 w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 29 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0x36 (54) maximum analog gain 6:0 maximum analog gain this register is used by the automatic gain control (agc) as the upper threshold of gain. this ensures the new calibrated gain value does not exceed that which the mt9v032 supports. range: 16 dec C64 dec for 1xC4x respectively. note: no exception detection is installed; caution should be taken when programming. 40 (64) y 16C64 w 0x42 (66) frame dark average 7:0 frame dark average the value read is the frame averaged black level, that is, used in the black level algorithm calculations. 0r 0x46 (70) dark average thresholds 7:0 lower threshold lower threshold for targeted black level in adc lsbs. 1d (29) n 0C255 w 15:8 upper threshold upper threshold for targeted black level in adc lsbs. 23 (35) n 0C255 w 0x47 (71) black level calibration control 0 manual override manual override of black level correction. 1 = override automatic black level correction with programmed values. (r0x48). 0 = normal operation (default). 0n0, 1w 7:5 frames to average over two to the power of this value decide how many frames to average over when the black level algorithm is in the averaging mode. in this mode the running frame average is calculated from the following formula: running frame ave = old running frame ave - (old running frame ave)/2n + (new frame ave)/ 2n. 4 n 0C7 w 15:8 reserved reserved. 80 (128) 0x48 (72) black level calibration value 7:0 black level calibration value analog calibration offset: negative numbers are represented with twos complement, which is shown in the following formula: sign = bit 7 (0 is positive, 1 is negative). if positive offset value: magnitude = bit 6:0. if negative offset value: magnitude = not (bit 6:0) + 1. during two-wire serial interface read, this register returns the user-programmed value when manual override is enabled (r0x47 bit 0); otherwise, this register returns the result obtained from the calibration algorithm. 0 n C127 to 127 w 0x4c (76) black level calibration value step size 4:0 step size of calibration value this is the size calibration value may change (positively or negatively) from frame to frame. 1 calib lsb = ? adc lsb, assuming analog gain = 1. 2 n 0C31 w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 30 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0x70 (112) row noise correction control 1 3:0 number of dark pixels the number of pixels used in the row-wise noise calculation. 0 = 2 pixels. 1 = 4 pixels. 2 = 6 pixels. 4 = 10 pixels. 8 = 18 pixels. see row-wise noise correction on page 49 for additional information. 4 y 0, 1, 2, 4, 8 w 4 reserved reserved. 1 5 enable noise correction 0 = normal operation. 1 = enable row noise cancellation algorithm. when this bit is set, on a per row basis, the dark average is subtracted from each pixel in the row, and then a constant (r0x72) is added. 1y0, 1w 11 use black level average 1 = use black level frame average from the dark rows in the row noise correction algorithm for low gains. this frame average was taken before the last adjustment of the offset dac for that frame, so it might be slightly off. 0 = use the average value of the dark columns read out in each row as dark average. 0y0, 1w 0x72 (114) row noise constant 7:0 row noise constant constant used in the row noise cancellation algorithm. it should be set to the dark level targeted by the black level algorithm plus the noise expected between the averaged values of dark columns. at default the constant is set to 42 lsb. 2a (42) y 0C255 w 0x73 (115) row noise correction control 2 9:0 dark start column address the starting column address for the dark columns to be used in the row-wise noise correction algorithm. 2f7 (759) y 759C775 w 0x74 (116) pixel clock, frame and line valid control 0 invert line valid invert line valid. when set, line_valid is reset to logic 0 when d out is valid. 0y0, 1w 1 invert frame valid invert frame valid. when set, frame_valid is reset to logic 0 when frame is valid. 0y0, 1w 2 xor line valid 1 = line valid = "continuous" line valid xor frame valid 0 = line valid determined by bit 3. ineffective if continuous line valid is set. 0y0, 1w 3 continuous line valid 1 = "continuous" line valid (continue producing line valid during vertical blank). 0 = normal line valid (default, no line valid during vertical blank). 0y0, 1w 4 invert pixel clock invert pixel clock. when set, line_valid, frame_valid, and d out is set up to the rising edge of pixel clock, pixclk. when clear, they are set up to the falling edge of pixclk. 0y0, 1w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 31 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0x7f (127) digital test pattern 9:0 two-wire serial interface test data the 10-bit test data in this register is used in place of the data from the sensor. the data is inserted at the beginning of the digital signal processing. both test enable (bit 13) and use two-wire serial interface (bit 10) must be set. 0 n 0C1023 w 10 use two-wire serial interface test data 0 = use gray shade test pattern as test data. 1 = use two-wire serial interface test data (bits 9:0) as test data. 0n0, 1w 12:11 gray shade test pattern 0 = none. 1 = vertical shades. 2 = horizontal shades. 3 = diagonal shade. when bits (12:11) 0, the mt9v032 generates a gray shaded test pattern to be used as digital test data. ineffective when use two-wire serial interface test data (bit 10) is set. 0 n 0C3 w 13 test enable enable the use of test data/gray shaded test pattern in the signal chain. the data is inserted instead of data from the adcs. set r0x70 bit 5 = 0 when using this mode. if r0x70 bit 5 = 1, the row-wise correction algorithm processes the test data values and the result is not accurate. 0y0, 1w 14 flip two-wire serial interface test data use only when two-wire serial interface test data (bit 10) is set. when set, the two-wire serial interface test data (bits 9:0) is used in place of the data from adc/ memory on odd columns, while complement of the two-wire serial interface test data is used on even columns. 0n0, 1w 0x80 (128) - 0x98 (152) tiled digital gain 3:0 tile gain tile digital gain = bits (3:0) x 0.25. see gain settings on page 46 for additional information on digital gain. 4 y 1C15 w 7:4 sample weight to indicate the weight of individual tile used in the automatic gain/exposure control algorithm. f (15) y 0C15 w refer to figure 25 on page 47 for r0x99 (153) - r0xa4 (164). 0x99 (153) digital tile coordinate 1 - x-direction 9:0 x 0/5 the starting x-coordinate of digital tiles x0_*. 0 y 0C752 w 0x9a (154) digital tile coordinate 2 - x-direction 9:0 x 1/5 the starting x-coordinate of digital tiles x1_*. 096 (150) y 0C752 w 0x9b (155) digital tile coordinate 3 - x-direction 9:0 x 2/5 the starting x-coordinate of digital tiles x2_*. 12c (300) y 0C752 w 0x9c (156) digital tile coordinate 4 - x-direction 9:0 x 3/5 the starting x-coordinate of digital tiles x3_*. 1c2 (450) y 0C752 w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 32 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0x9d (157) digital tile coordinate 5 - x-direction 9:0 x 4/5 the starting x-coordinate of digital tiles x4_*. 258 (600) y 0C752 w 0x9e (158) digital tile coordinate 6 - x-direction 9:0 x 5/5 the ending x-coordinate of digital tiles x4_*. 2f0 (752) y 0C752 w 0x9f (159) digital tile coordinate 1 - y-direction 8:0 y 0/5 the starting y-coordinate of digital tiles *_y0. 0 y 0C480 w 0xa0 (160) digital tile coordinate 2 - y-direction 8:0 y 1/5 the starting y-coordinate of digital tiles *_y1. 60 (96) y 0C480 w 0xa1 (161) digital tile coordinate 3 - y-direction 8:0 y 2/5 the starting y-coordinate of digital tiles *_y2. 0c0 (192) y 0C480 w 0xa2 (162) digital tile coordinate 4 - y-direction 8:0 y 3/5 the starting y-coordinate of digital tiles *_y3. 120 (288) y 0C480 w 0xa3 (163) digital tile coordinate 5 - y-direction 8:0 y 4/5 the starting y-coordinate of digital tiles *_y4. 180 (384) y 0C480 w 0xa4 (164) digital tile coordinate 6 - y-direction 8:0 y 5/5 the ending y-coordinate of digital tiles *_y4. 1e0 (480) y 0C480 w 0xa5 (165) aec/agc desired bin 5:0 desired bin user-defined desired bin that gives a measure of how bright the image is intended. 3a (58) y 1C64 w 0xa6 (166) aec update frequency 3:0 exp skip frame the number of frames that the aec must skip before updating the exposure register (r0xbb). 2 y 0C15 w 0xa8 (168) aec low pass filter 1:0 exp lpf this value plays a role in determining the increment/ decrement size of exposure value from frame to frame. if current bin 0 (r0xbc), when exp lpf = 0: actual new exposure = calculated new exposure when exp lpf = 1: if |(calculated new exp - current exp) | > (current exp/4), actual new exposure = calculated new exposure, otherwise actual new exposure = current exp (calculated new exp/2) when exp lpf = 2: if |(calculated new exp - current exp) |> (current exp/4), actual new exposure = calculated new exposure, otherwise actual new exposure = current exp (calculated new exp/4) 2 y 0C2 wx table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 33 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0xa9 (169) agc output update frequency 3:0 gain skip frame the number of frames that the agc must skip before updating the gain register (r0xba). 2 y 0C15 w 0xab (171) agc low pass filter 1:0 gain lpf this value plays a role in determining the increment/ decrement size of gain value from frame to frame. if current bin 0 (r0xbc) when gain lpf = 0: actual new gain = calculated new gain when exp lpf = 1: if |(calculated new gain - current gain) | > (current gain/ 4), actual new gain = calculated new gain, otherwise actual new gain = current exp (calculated new gain/ 2) when exp lpf = 2: if |(calculated new gain - current gain) | > (current gain / 4), actual new gain = calculated new gain, otherwise actual new gain = current gain (calculated new gain/ 4). 2 y 0C2 w 0xaf (175) agc/aec enable 0 aec enable 0 = disable automatic exposure control. 1 = enable automatic exposure control. 1y0, 1w 1 agc enable 0 = disable automatic gain control. 1 = enable automatic gain control. 1y0, 1w 0xb0 (176) agc/aec pixel count 15-0 pixel count the number of pixel used for the aec/agc histogram. abe0 (44,000) y 0C65535 w 0xb1 (177) lvds master control 0 pll bypass 0 = internal shift-clk is driven by pll. 1 = internal shift-clk is sourced from the lvds_bypass_clk. 0y0, 1w 1 lvds power-down 0 = normal operation. 1 = power-down lvds block. 1y0, 1w 2 pll test mode 0 = normal operation. 1 = the pll output frequency is equal to the system clock frequency (26.6 mhz). 0y0, 1w 3 lvds test mode 0 = normal operation. 1 = the ser_dataout_p drives a square wave in both stereo and stand-alone modes). in stereo mode, ensure that ser_datain_p is logic 0. 0y0, 1w 0xb2 (178) lvds shift clock control 2:0 shift-clk delay element select the amount of shift-clk delay that minimizes inter- sensor skew. 0 y 0C7 w 4 lvds receiver power-down when set, lvds receiver is disabled. 1 y 0, 1 w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 34 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0xb3 (179) lvds data control 2:0 data delay element select the amount of data delay that minimizes inter-sensor skew. 0 y 0C7 w 4 lvds driver power-down when set, data lvds driver is disabled. 1 y 0, 1 w 0xb4 (180) lvds latency 1:0 stream latency select the amount of delay so that the two streams are in sync. 0 y 0C3 w 0xb5 (181) lvds internal sync 0 lvds internal sync enable when set, the mt9v032 generates sync pattern (data with all zeros except start bit) on lvds_ser_data_out. 0y0, 1w 0xb6 (182) lvds payload control 0 use 10-bit pixel enable when set, all 10 pixel data bits are output in stand- alone mode. control signals are embedded. if clear, 8 bits of pixel data are output with 2 control bits. see lvds output format on page 57 for additional information. 0y0, 1w 0xb7 (183) stereoscopy error control 0 enable stereo error detect set this bit to enable stereo error detect mechanism. 0 y 0, 1 w 1enable stick stereo error flag when set, the stereo error flag remains asserted once an error is detected unless clear stereo error flag (bit 2) is set. 0y0, 1w 2 clear stereo error flag set this bit to clear the stereoscopy error flag (r0xb8 returns to logic 0). 0y0, 1w 0xb8 (184) stereoscopy error flag 0 stereoscopy error flag stereoscopy error status flag. it is also directly connected to the error output pin. r 0xb9 (185) lvds data output 15:0 combo reg this 16-bit value contains both 8-bit pixel values from both stereoscopic master and slave sensors. it can be used in diagnosis to determine how well in sync the two sensors are. captures the state when master sensor has issued a reserved byte and slave has not. note: this register should be read from the stereoscopic master sensor only. r 0xba (186) agc gain output 6:0 agc gain status register to report the current gain value obtained from the agc algorithm. 10 (16) r 0xbb (187) aec exposure output 15:0 aec exposure status register to report the current exposure value obtained from the aec algorithm. 00c8 (200) r 0xbc (188) agc/aec current bin 5:0 current bin status register to report the current bin of the histogram. r table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 35 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0xbd (189) maximum total shutter width 15:0 maximum total shutter width this register is used by the automatic exposure control (aec) as the upper threshold of exposure. this ensures the new calibrated integration value does not exceed that which the mt9v032 supports. 01e0 (480) y 1C2047 w 0xbe (190) agc/aec bin difference threshold 7:0 bin difference threshold this register is used by the aec only when exposure reaches its minimum value of 1. if the difference between desired bin (r0xa5) and current bin (r0xbc) is larger than the threshold, the exposure is increased. 14 (20) y 0C63 w 0xbf (191) field vertical blank 8:0 field vertical blank the number of blank rows between odd and even fields. note: for interlaced (both field) mode only. see r0x07[2:0]. 16 (22) y 0C255 w 0xc0 (192) monitor mode capture control 7:0 image capture numb the number of frames to be captured during the wake- up period when monitor mode is enabled. 0a (10) y 0C255 w 0xc1 (193) thermal information 9:0 temperature output status register to report the temperature of sensor. updated once per frame. r 0xc2 (194) analog controls 6 reserved reserved. 1 n 0, 1 w 7 anti-eclipse enable setting this bit turns on anti-eclipse circuitry. 0 n 0, 1 w 11:13 v_rst_lim voltage level v_rst_lim = bits (2:0) 50mv + 1.95v range: 1.95C2.30v; default: 2.00v usage: for anti-eclipse reference voltage control 1 n 0C7 w 0xc3 (195) ntsc frame valid control 0extend frame valid when set, frame valid is extended for half-line in length at the odd field. 0y0, 1w 1replace fv/lv with ped/snyc when set, frame valid and line valid is replaced by ped and sync signals respectively. 0y0, 1w 0xc4 (196) ntsc horizontal blanking control 7:0 front porch width the front porch width in number of master clock cycle. ntsc standard is 1.5 sec 0.1 sec 16 (22) y 0C255 w 15:8 sync width the sync pulse width in number of master clock cycle. ntsc standard is 4.7 sec 0.1 sec. 044 (68) y 0C255 w 0xc5 (197) ntsc vertical blanking control 7:0 equalizing pulse width the pulse width in number of master clock cycle. ntsc standard is 2.3 sec 0.1 sec. 21 (33) y 0C255 w 15:8 vertical serration width the pulse width in number of master clock cycle. ntsc standard is 4.7 sec 0.1 sec. 44 (68) y 0C255 w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 36 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor registers 0xf0 (240) bytewise address bytewise address special address to perform 8-bit reads and writes to the sensor. see the "two- wire serial interface sample read and write sequences " on page 17 for further details on how to use this functionality. 0xfe (254) register lock 15:0 register lock code to lock all registers except r0xfe, program data with 0xdead; to unlock two-wire serial interface, program data with 0xbeef. when two-wire serial interface is locked, any subsequent two-wire serial interface write to register other than to two-wire serial interface protect enable register is ignored until two-wire serial interface is unlocked. to lock register 13 only, program data with 0xdeaf; to unlock, program data with 0xbeef. when register 13 is locked, any subsequent two-wire serial interface write to this register only is ignored until register is unlocked. beef (48879) n 48879, 57005, 57007 w table 8: register descriptions (continued) bit bit name bit description default in hex (dec) shadowed legal values (dec) read/ write
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 37 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description feature description operational modes the mt9v032 works in master, snapshot, or slave mode. in master mode the sensor generates the readout timing. in snapshot mode it accepts an external trigger to start integration, then generates the readout timi ng. in slave mode the sensor accepts both external integration and readout controls. th e integration time is programmed through the two-wire serial interface during master or snapshot modes, or controlled through externally generated control signal during slave mode. master mode there are two possible operation methods fo r master mode: simultaneous and sequen- tial. one of these operation modes must be selected through the two-wire serial inter- face. simultaneous master mode in simultaneous master mode, the exposure period occurs during readout. the frame synchronization waveforms are shown in figure 13 and figure 14. the exposure and readout happen in parallel rather than sequentially, making this the fastest mode of operation. figure 13: simultaneous master mode synchronization waveforms #1 figure 14: simultaneous master mode synchronization waveforms #2 readout time > exposure time led_out d out (9:0) line_valid frame_valid exposure time vertical blanking xxx xxx xxx exposure time > readout time led_out d out (9:0) line_valid frame_valid exposure time vertical blanking xxx xxx xxx
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 38 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description when exposure time is greater than the su m of vertical blank and window height, the number of vertical blank rows is increase d automatically to accommodate the exposure time. sequential master mode in sequential master mode the exposure period is followed by readout. the frame synchronization waveforms for sequential master mode are shown in figure 15. the frame rate changes as the integration time changes. figure 15: sequential master mode synchronization waveforms snapshot mode in snapshot mode the sensor accepts an input trigger signal which initiates exposure, and is immediately followed by readout. figure 16 shows the interface signals used in snapshot mode. in snapshot mode, the start of the integration period is determined by the externally applied exposure pulse that is input to the mt9v032. the integration time is preprogrammed via the two-wire serial interface on r0x0b. after the frame's inte- gration period is complete the readout pr ocess commences and the syncs and data are output. sensor in snapshot mode can captur e a single image or a sequence of images. the frame rate may only be controlled by changing the period of the user supplied exposure pulse train. the frame synchron ization waveforms for snapshot mode are shown in figure 17. figure 16: snapshot mode interface signals led_out d out (9:0) line_valid frame_valid exposure time xxx xxx xxx controller exposure sysclk pixclk line_valid frame_valid d out (9:0) mt9v032
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 39 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description figure 17: snapshot mode frame synchronization waveforms slave mode in slave mode, the exposure and readout are controlled using the exposure, stfrm_out, and stln_out pins. when the slave mode is enabled, stfrm_out and stln_out become input pins. the start and end of integration are contro lled by exposure and stfrm_out pulses, respectively. while a stfrm_out pulse is used to stop integration, it is also used to enable the readout process. after integration is stopped, the user provid es stln_out pulses to trigger row readout. a full row of data is read out with each stln_out pulse. the user must provide enough time between successive stln_o ut pulses to allow the comp lete readout of one row. it is also important to provide additional st ln_out pulses to allow the sensors to read the vertical blanking rows. it is recommended that the user program the vertical blank register (r0x06) with a value of 4, and ac hieve additional vertic al blanking between frames by delaying the application of the stfrm_out pulse. the elapsed time between the rising edge of stln_out and the first valid pixel data is [horizontal blanking register (r0x05) + 4] clock cycles. figure 18: slave mode operation led_out d out (9:0) line_valid frame_valid exposure time xxx xxx xxx exposure 1-ro w time 2 master clocks 1-ro w time 98 ma ster clocks exposure (input) stfrm_out (input) led_out (output) stln_out (input) line_v alid (output) integration t ime vertical blanking (def = 45 lines)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 40 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description signal path the mt9v032 signal path consists of a programmable gain, a pr ogrammable analog offset, and a 10-bit adc. see ?black leve l calibration? on page 48 for the programmable offset operation description. figure 19: signal path on-chip biases adc voltage reference the adc voltage reference is programmed th rough r0x2c, bits 2:0. the adc reference ranges from 1.0v to 2.1v. the default value is 1.4v. the increment size of the voltage reference is 0.1v from 1.0v to 1.6v (r0x2c[2:0] values 0 to 6). at r0x2c[2:0] = 7, the refer- ence voltage jumps to 2.1v. the effect of the adc calibration does not scale with v ref . instead it is a fixed value rela- tive to the output of the analog gain stage. at default, one lsb of calibration equals two lsb in output data (1lsb offset = 2mv, 1lsb adc = 1mv). it is very important to preserve the correct va lues of the other bits in r0x2c. the default register setting is 0x0004. v_step voltage reference this voltage is used for pixel high dynamic range operations, programmable from r0x31 through r0x34. chip version chip version registers r0x 00 and r0xff are read-only. window control registers r0x01 column start, r0x02 row star t, r0x03 window height (row size), and r0x04 window width (column size ) control the size and star ting coordinates of the window. the values programmed in the window height and width registers are the exact window height and width out of the sensor. the wind ow start value should never be set below four. pixel output (reset minus signal) offset correction voltage (r0x48 or result of blc) 10 (12) bit adc adc data (9:0) gain selection (r0x35 or result of agc) v ref (r0x2c) c2 c1
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 41 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description to read out the dark rows set bit 6 of r0x0d. in addition, bit 7 of r0x0d can be used to display the dark columns in the image. blanking control horizontal blanking and vertical blanking re gisters r0x05 and r0x06 respectively control the blanking time in a row (horizontal blanking) and between frames (vertical blanking). ? horizontal blanking is specified in terms of pixel clocks. ? vertical blanking is specified in terms of numbers of rows. the actual imager timing ca n be calculated using table 4 on page 13 and table 5 on page 14 which describe ?row timing and frame_valid/line_valid signals.? the minimum number of vertical blank rows is 4.
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 42 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description pixel integration control total integration r0x0b total shutter width (in terms of number of rows) this register (along with the window width and horizontal blanking registers) controls the integration time for the pixels. the actual total integration time, t int, is: t int = (number of rows of integration row time) + overhead (eq 1) where: ? the number of rows integration is equal to the result of automatic exposure control (aec) which may vary from frame to frame, or, if aec is disabled, the value in r0x0b ? row time = (r0x04 + r0x05) master clock periods ? overhead = (r0x04 + r0x05 ? 255) master clock periods typically, the value of r0x0b (total shutter wi dth) is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. if r0x0b is increased beyo nd the total number of rows per frame, it is required to add additional blanking rows using r0x06 as needed. a second constraint is that t int must be adjusted to avoid banding in the image from light flicker. under 60hz flicker, this means frame time must be a multiple of 1/120 of a second. under 50hz flicker, frame time must be a multiple of 1/100 of a second. changes to integration time with automatic exposure control disabled (r 0xaf, bit 0 is cleared to low), and if the total integration time (r0x0b) is changed th rough the two-wire se rial interface while frame_valid is asserted for frame n , the first frame output using the new integration time is frame ( n + 2 ). similarly, when automatic exposu re control is enabled, any change to the integration time for frame n first appears in frame ( n + 2 ) output. the sequence is as follows: 1. during frame n , the new integration time is held in the r0x0b live register. 2. at the start of frame ( n + 1 ), the new integration time is transferred to the exposure control module. integration for each row of frame ( n + 1 ) has been completed using the old integration time. the earliest time that a row can start integrating using the new integration time is immediately afte r that row has been read for frame ( n + 1 ). the actual time that rows start integratin g using the new integration time is depen- dent on the new value of the integration time. 3. when frame ( n + 1 ) is read out, it is integrated using the new integration time. if the integration time is changed (r0x0b written) on successive frames, each value written is applied to a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. however, when automatic exposure control is disabled, if the integration time is changed through the two-wire serial interf ace after the falling edge of frame_valid for frame n , the first frame output using the new integration time becomes frame ( n+3 ).
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 43 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description figure 20: latency when changing integration exposure indicator the exposure indicator is controlled by: ?r0x1b led_out control the mt9v032 provides an output pin, led_out, to indicate when the exposure takes place. when r0x1b bit 0 is clear, led_out is high during exposure. by using r0x1b, bit 1, the polarity of the led_out pin can be inverted. high dynamic range high dynamic range is controlled by: ?r0x08 shutter width 1 ?r0x09 shutter width 2 ? r0x0a shutter width control ?r0x31 ? r0x34 v_step voltages in the mt9v032, high dynamic range (that is, r0 x0f, bit 6 = 1) is achieved by controlling the saturation level of the pixel (hdr or high dynamic range gate) during the exposure period. the sequence of the control voltages at the hdr gate is shown in figure 21. after the pixels are reset, the step voltage, v_step, which is applied to hdr gate, is set up at v1 for integration time t 1 then to v2 for time t 2 , then v3 for time t 3 , and finally it is parked at v4, which also serves as an antiblooming volt age for the photodetector. this sequence of voltages leads to a piecewise linear pixel response, illustrated (in approximates) in figure 21 on page 44. frame_valid image data frame start led_out output image with int = 200 rows output image with int = 300 rows int = 300 rows int = 200 rows int = 200 rows int = 300 rows new integration programmed actual integration
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 44 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description figure 21: sequence of control voltages at the hdr gate figure 22: sequence of voltages in a piecewise linear pixel response the parameters of the step voltage v_step which takes values v1, v2, and v3 directly affect the position of the knee points in figure 22. light intensities work approximately as a reci procal of the partial exposure time. typi- cally, t 1 is the longest exposure, t 2 shorter, and so on. thus the range of light intensities is shortest for the first slope, providing the highest sensitivity. the register settings for v_step and partial exposures are: v1 = r0x31, bits 4:0 v2 = r0x32, bits 4:0 v3 = r0x33, bits 4:0 v4 = r0x34, bits 4:0 t int = t 1 + t 2 + t 3 there are two ways to specify the knee points timing, the first by ma nual setting (default) and the second by automatic knee point adjustment. when the auto adjust enabler is set to high (low by default), the mt9v032 calculates the knee points automatically using the following equations: t 1 = t int - t 2 - t 3(eq 2) t 2 = t int x (?) r0x0a, bits 3:0 (eq 3) t 3 = t int x (?) r0x0a, bits 7:4 (eq 4) as a default for auto exposure, t 2 is 1/16 of t int, t 3 is 1/64 of t int. t 2 t 3 v4~0.8v exposure t 1 hdr voltage v aa (3.3v) v1~1.4v v2~1.2v v3~1.0v dv1 dv2 dv3 1/t 1 1/t 2 1/t 3 light intensity output
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 45 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description when the auto adjust enabler is disabled (default), t 1, t 2, and t 3 may be programmed through the two-wire serial interface: t 1 = r0x08, bits 14:0 (eq 5) t 2 = (r0x09, bits 14:0) - (r0x08, bits 14:0) (eq 6) t 3 = t int - t 1 - t 2(eq 7) t int may be based on the manual setting of r0x0 b or the result of the aec. if the aec is enabled then the auto knee adjust must also be enabled. variable adc resolution by default, adc resolution of the sensor is 10-bit. addition ally, a companding scheme of 12-bit into 10-bit is enabled by the r0x1c (2 8). this mode allows higher adc resolution which means less quantization noise at low-li ght, and lower resolution at high light, where good adc quantization is not so critical because of the high level of the photon?s shot noise. figure 23: 12- to 10-bit companding chart 256 512 768 1,024 4,096 2,048 1,024 512 256 4 to 1 companding (1,536 384) -8 to 1 companding (2,048 256) 10-bit codes 12-bit codes 2 to 1 companding (256 128) no companding (256 256)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 46 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description gain settings changes to gain settings when the digital gain settings (r0x80 ? r0x98) are changed, the gain is updated on the next frame start. however, the latency for an analog gain change to take effect depends on the automatic gain control. if automatic gain control is enabled (r0xaf, bit 1 is set to high), the gain changed for frame n first appears in frame ( n + 1 ); if the automatic gain control is disabled, the gain changed for frame n first appears in frame ( n + 2 ). both analog and digital gain change regardless of whether the integration time is also changed simultaneously. figure 24: latency of analog gain change when agc is disabled analog gain analog gain is controlled by: ? r0x35 global gain the formula for gain setting is: gain = bits[6:0] x 0.0625 (eq 8) the analog gain range supported in the mt9v032 is 1x ? 4x with a step size of 6.25 percent. to control gain manually with this register, the sensor must not be in agc mode. when adjusting the luminosity of an im age, it is recommended to alter exposure first and yield to gain increases only when the exposure value has reached a maximum limit. analog gain = bits (6:0) x 0.0625 for values 16?31 (eq 9) analog gain = bits (6:0)/2 x 0.125 for values 32?64 (eq 10) for values 16?31: each lsb increases analog gain 0.0625v/v. a value of 16 = 1x gain. range: 1x to 1.9375x. for values 32?64: each 2 lsb increases analog gain 0.125v/v (that is, double the gain increase for 2 lsb). range: 2x to 4x. odd values do not result in gain increases; the gain increases by 0.125 for values 32, 34, 36, and so on. frame_valid image data frame start output image with gain = 3.0x output image with gain = 3.5x gain = 3.0x gain = 3.5x gain = 3.0x gain = 3.5x new gain programmed actual gain
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 47 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description digital gain digital gain is controlled by: ?r0x99 ? r0xa4 tile coordinates ?r0x80 ? r0x98 tiled digital gain and weight in the mt9v032, the image may be divided into 25 tiles, as shown in figure 25, through the two-wire serial interface, and apply digital gain individually to each tile. figure 25: tiled sample registers 0x99 ? 0x9e and 0x9f ? 0xa4 represent the coordinates x 0/5 -x 5/5 and y 0/5 -y 5/5 in figure 25, respectively. digital gains of registers 0x80 ? 0x98 apply to their corresponding tiles. the mt9v032 supports a digital gain of 0.25-3.75x. the formula for digital gain setting is: digital gain = bits[3:0] x 0.25 (eq 11) x 0/5 x 1/5 x 2/5 x 3/5 x 5/5 x 5/5 y 0/5 y 1/5 y 2/5 y 3/5 y 4/5 y 5/5 x0_y0 x1_y0 x4_y0 x0_y1 x1_y1 x4_y1 x0_y2 x1_y2 x4_y2 x0_y3 x1_y3 x4_y3 x0_y4 x1_y4 x4_y4
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 48 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description black level calibration black level calibration is controlled by: ?r0x4c ?r0x42 ? r0x46?r0x48 the mt9v032 has automatic black level calibration on-chip, and if enabled, its result may be used in the offset correction shown in figure 26. figure 26: black level calibration flow chart the automatic black level calibration measures the average value of pixels from 2 dark rows (1 dark row if row bin 4 is enabled) of the chip. (the pixels are averaged as if they were light-sensitive and passed through the appropriate gain.) this row average is then digitally low-pass fi ltered over many frames (r0x47, bits 7:5) to remove temporal noise and random instabil ities associated with this measurement. then, the new filtered average is compar ed to a minimum acceptable level, low threshold, and a maximum accept able level, high threshold. if the average is lower than the minimum acce ptable level, the offset correction voltage is increased by a programmable offset lsb in r0x4c. (default step size is 2 lsb offset = 1 adc lsb at analog gain = 1x.) if it is above the maximum level, the offset correction voltage is decreased by 2 lsb (default). to avoid oscillation of the black level from below to above, the region the thresholds should be programmed so the difference is at least two times the offset dac step size. in normal operation, the black level calibration value/offset correction value is calcu- lated at the beginning of each frame and can be read through the two-wire serial inter- face from r0x48. this register is an 8-bit signed two?s complement value. however, if r0x47, bit 0 is set to ?1,? the calibration value in r0x48 may be manually set to override the automatic black level calcul ation result. this feature can be used in conjunction with the ?show dark rows? feature (r0x0d, bit 6) if using an external black level calibration circuit. pixel output (reset minus signal) offset correction voltage (r0x48 or result of blc) 10 (12) bit adc adc data (9:0) gain selection (r0x35 or result of agc) v ref (r0x2c) c2 c1
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 49 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description the offset correction voltage is generated according to the following formulas: offset correction voltage = (8-bit signed two?s complement calibration value,-127 to 127) 0.5mv (eq 12) adc input voltage = (pixel output voltage + offset correction voltage) analog gain (eq 13) row-wise noise correction row-wise noise correction is controlled by the following registers: ? r0x70 row noise control ? r0x72 row noise constant ?r0x73 dark column start when the row-wise noise cancellation algori thm is enabled, the average value of the dark columns read out is used as a correction for the whole row. the row-wise correction is in addition to the general black level correction applied to the whole sensor frame and cannot be used to replace the latter. the dark average is subtracted from each pixel belonging to the same row, and then a positi ve constant is added (r0x72, bits 7:0). this constant should be set to the dark level ta rgeted by the black level algorithm plus the noise expected on the measurements of the averaged values from dark columns; it is meant to prevent clipping from negative noise fluctuations. pixel value = adc value - dark column average + row noise constant (eq 14) on a per-row basis, the dark column aver age is calculated fr om a programmable number of dark columns (pixels) values (r0x70 , bits 3:0). the default is 10 dark columns. of these, the maximum and minimum values are removed and then the average is calcu- lated. if r0x70, bits 3:0 are set to ?0? (2 pixels), it is essentially equivalent to disabling the dark average calculation since the averag e is equal to ?0? after the maximum and minimum values are removed. r0x73 is used to indicate the starting column address of dark pixels that the row-noise correction algorithm uses for calculation. in the mt9v032, dark columns which may be used are 759?776. r0x73 is us ed to select the starting column for the calculation. one additional note in setting the row-noise correction register: 777 < (r0x73, bits 9:0) + number of dark pixels programmed in r0x70, bits 3:0 -1 (eq 15) this is to ensure the column pointer does not go beyond the limit the mt9v032 can support.
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 50 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description automatic gain control and automatic exposure control the integrated aec/agc unit is responsible fo r ensuring that optimal auto settings of exposure and (analog) gain are computed and updated every frame. automatic exposure control (aec) and automati c gain control (agc) can be individually enabled or disabled by r0xaf. when aec is disabled (r0xaf[0] = 0), the sensor uses the manual exposure value in r0x0b. when agc is disabled (r0xaf[1] = 0), the sensor uses the manual gain value in r0x35. see aptina technical note tn-09-81, ?mt9v032 aec and agc functions,? for further details . figure 27: controllable and observable aec/agc registers the exposure is measured in row-time by reading r0xbb. the exposure range is 1 to 2047. the gain is measured in gain-units by reading r0xba. the gain range is 16 to 63 (unity gain = 16 gain-units; multiply by 1/16 to get the true gain). when aec is enabled (r0xaf[0] = 1), the ma ximum auto exposure value is limited by r0xbd; minimum auto exposure is fixed at 1 row. when agc is enabled (r0xaf[1] = 1), the maximum auto gain value is limited by r0x36; minimum auto gain is fixed to 16 gain-units. the exposure control measures current scene luminosity and desired output luminosity by accumulating a histogram of pixel valu es while reading out a frame. the desired exposure and gain are then calculated from this for subsequent frame. pixel clock speed the pixel clock speed is same as the master clock (sysclk) at 26.66 mhz by default. however, when column binning 2 or 4 (r0x0d , bit 2 or 3) is enab led, the pixel clock speed is reduced by half and one-fourth of the master clock speed respectively. see ?read mode options? on page 52 and ?column binning? on page 54 for additional infor- mation. exp. lpf (r0xa8) 1 0 1 0 exp. skip (r0xa6) manual exp. (r0x0b) aec enable (r0xaf[0]) max. exposure (r0xbd) min exp. aec unit to exposure timing control aec output r0xbb r0xba to analog gain control histogram generator unit agc unit gain lpf (r0xab) gain skip (r0xa9) manual gain (r0x35) agc enable (r0xaf[1]) agc output max. gain (r0x36) min gain desired bin (desired luminance) (r0xa5) current bin (current luminance) (r0xbc) 1 16
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 51 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description hard reset of logic the rc circuit for the mt9v032 uses a 10k resistor and a 0.1 f capacitor. the rise time for the rc circuit is 1 s maximum. soft reset of logic soft reset of logic is controlled by: ?r0x0c reset bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire serial interface configuration. furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and star ts a new frame. bit 1 is a shadowed reset control register bit to explicitly reset the automatic gain and exposure control feature. these two bits are self-resetting bits and also return to ?0? during two-wire serial inter- face reads. standby control the sensor goes into standby mode by setting standby to high. once the sensor detects that standby is asserted, it comple tes the current frame before disabling the digital logic, internal clocks, and analog power enable signal. to release the sensor from the standby mode, reset standby back to low. the lvds must be powered to ensure that the device is in standby mode. see "appendix b ? power-on reset and standby timing" on page 71 for more information on standby. monitor mode control monitor mode is controlled by: ? r0x0e monitor mode enable ? r0xc0 monitor mode image capture control the sensor goes into monitor mode when r0x0e bit 0 is set to high. in this mode, the sensor first captures a programmable number of frames (r0xc0), then goes into a sleep period for five minutes. the cycle of sleeping for five minutes and waking up to capture a number of frames continues until r0x0e bit 0 is cleared to return to normal operation. in some applications when monitor mode is enabled, the purpose of capturing frames is to calibrate the gain and exposure of the scene using automatic gain and exposure control feature. this feature typically takes less than 10 frames to settle. in case a larger number of frames is needed, the value of r0xc0 may be increased to capture more frames. during the sleep period, none of the analog ci rcuitry and a very small fraction of digital logic (including a five-minute timer) is powered. the master clock (sysclk) is therefore always required.
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 52 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description read mode options (also see ?output data format? on page 12 and ?output data timing? on page 13.) column flip by setting bit 5 of r0x0d the readout order of the columns is reversed, as shown in figure 28 on page 52. row flip by setting bit 4 of r0x0d the readout order of the rows is reversed, as shown in figure 29 on page 52. figure 28: readout of 6 pixels in normal and column flip output mode figure 29: readout of 6 rows in normal and row flip output mode pixel binning in addition to windowing mode in which smaller resolution (cif, qcif) is obtained by selecting small window from the sensor array, the mt9v032 also provides the ability to show the entire image captured by pixel array with smaller resolution by pixel binning. pixel binning is based on combining signals from adjacent pixels by averaging. there are two options: binning 2 and binning 4. when bi nning 2 is on, 4 pixel signals from 2 adja- cent rows and columns are combined. in binning 4 mode, 16 pixels are combined from 4 adjacent rows and columns. the image mode may work in conjunction with image flip. the binning operation increases snr but decreases resolution. enabling row bin2 and row bin4 improves frame rate by 2x and 4x respectively. the feature of column binning does not increase the frame rate in less resolution modes. line_valid normal readout d out (9:0) reverse readout d out (9:0) p4,1 (9:0) p4,n (9:0) p4,n-1 (9:0) p4,n-2 (9:0) p4,n-3 (9:0) p4,n-4 (9:0) p4,n-5 (9:0) p4,2 (9:0) p4,3 (9:0) p4,4 (9:0) p4,5 (9:0) p4,6 (9:0) line_valid normal readout d out (9:0) reverse readout d out (9:0) row4 (9:0) row5 (9:0) row6 (9:0) row7 (9:0) row8 7(9:0) row9 (9:0) row484 (9:0) row483 (9:0) row482 (9:0) row481 (9:0) row480 7(9:0) row479 (9:0)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 53 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description row binning by setting bit 0 or 1 of r0x0d, only half or one-fourth of the row set is read out, as shown in figure 30 below. the number of rows read out is half or one-fourth of what is set in r0x03. figure 30: readout of 8 pixels in normal and row bin output mode line_valid normal readout d out (9:0) row4 (9:0) row5 (9:0) row6 (9:0) row7 (9:0) row8 (9:0) row9 (9:0) row10 (9:0) row11 (9:0) line_valid row bin 2 readout d out (9:0) row4 (9:0) row6 (9:0) row8 (9:0) line_valid row bin 4 readout d out (9:0) row4 (9:0) row8 (9:0) row10 (9:0)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 54 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description column binning in setting bit 2 or 3 of r0x0d, the pixel data ra te is slowed down by a factor of either two or four, respectively. this is due to the overhe ad time in the digital pixel data processing chain. as a result, the pixel clock speed is also reduced accordingly. figure 31: readout of 8 pixels in normal and column bin output mode line_valid normal readout d out (9:0) pixclk d out (9:0) pixclk d out (9:0) pixclk d1 (9:0) d2 (9:0) d3 (9:0) d4 (9:0) d5 (9:0) d6 (9:0) d7 (9:0) d8 (9:0) line_valid column bin 2 readout d12 (9:0) d34 (9:0) d56 (9:0) d78 (9:0) line_valid column bin 4 readout d out (9:0) d1234 (9:0) d5678 (9:0)
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 55 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description interlaced readout the mt9v032 has two interlaced readout options. by setting r0x07[2:0] = 1, all the even- numbered rows are read out first, followed by a number of programmable field blanking (r0xbf, bits 7:0), and then the odd-number ed rows and finally vertical blanking (minimum is 4 blanking rows). by setting r0x07[2:0] = 2, only one field is read out; consequently, the number of rows read out is half what is set in r0x03. the row start address (r0x02) determines which field gets read out; if the row start address is even, the even field is read out; if row start ad dress is odd, the odd field is read out. figure 32: spatial illustration of interlaced image readout when interlaced mode is enabled, the total number of blanking rows are determined by both field blanking register (r0xbf) and vert ical blanking register (r0x06). the follow- ings are their equations. field blanking = r0xbf, bits 7:0 (eq 16) vertical blanking = r0x06, bits 8:0 -r0xbf, bits 7:0 (eq 17) with minimum vertical blanking requirement = 4 (eq 18) similar to progressive scan, frame_valid is logic low during the valid image row only. binning should not be used in co njunction with interlaced mode. p 4,1 p 4,2 p 4,3 .....................................p 4,n-1 p 4,n p 6,0 p 6,1 p 6,2 .....................................p 6,n-1 p 6,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-2,0 p m-2,2 .....................................p m-2,n-2 p m-2,n p m,2 p m,2 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ............................................................................................. 00 00 00 00 00 00 ............................................................................................. 00 00 00 valid image - even field horizontal blanking vertical blanking p 5,1 p 5,2 p 5,3 .....................................p 5,n-1 p 5,n p 7,0 p 7,1 p 7,2 .....................................p 7,n-1 p 7,n p m-3,1 p m-3,2 .....................................p m-3,n-1 p m-3,n p m,1 p m,1 .....................................p m,n-1 p m,n valid image - odd field field blanking
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 56 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description line_valid by setting bit 2 and 3 of r0x74, the line_v alid signal can get three different output formats. the formats for reading out four rows and two vertical blanking rows are shown in figure 33. in the last format, the line_val id signal is the xor between the contin- uous line_valid signal and the frame_valid signal. figure 33: different line_valid formats lvds serial (stand-alone/stereo) output the lvds interface allows for the streaming of sensor data serially to a standard off-the- shelf deserializer up to five meters away fr om the sensor. the pixels (and controls) are packeted?12-bit packets for stand-alone mode and 18-bit packets for stereoscopy mode. all serial signalling (clk and data) is lvds. the lvds serial output could either be data from a single sensor (stand-alone) or stream-merged data from two sensors (self and its stereoscopic slave pair). the appendic es describe in detail the topologies for both stand-alone and stereoscopic modes. there are two standard deserializers that can be used. one for a stand-alone sensor stream and the other from a stereoscopic st ream. the deserializer attached to a stand- alone sensor is able to reproduce the standard parallel output (8-bit pixel data, line_valid, frame_valid and pixclk). the de serializer attached to a stereoscopic sensor is able to reproduc e 8-bit pixel data from each sensor (with embedded line_valid and frame_valid) and pixel-clk. an additional (simple) piece of logic is required to extract line_valid and frame_ valid from the 8-bit pixel data. irrespec- tive of the mode (stereoscopy/stand-alone ), line_valid and frame_valid are always embedded in the pixel data. in stereoscopic mode, the two sensors run in lock-step, implying all state machines are in the same state at any given time. this is ensured by the sensor-pair getting their sys- clks and sys-resets in the same instance. configuration writes through the two-wire serial interface are done in such a way th at both sensors can get their configuration updates at once. the inter-sensor serial link is designed in such a way that once the slave pll locks and the data-dly , shft-clk-dly and s tream-latency-sel are configured, the master sensor streams good stereo content ir respective of any variation voltage and/or temperature as long as it is within specification. the configuration values of data-dly , shft-clk-dly and stream-latency-sel are either predetermined from the board layout or can be empirically determined by reading back the stereo-error flag. this flag gets asserted when the two sensor streams are not in sync when merged. the combo_reg is used for out-of-sync diagnosis. def ault frame_valid line_valid continuously frame_valid line_valid xor frame_valid line_valid
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 57 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description figure 34: serial output format for a 6x2 frame note: 1. external pixel values of 0, 1, 2, 3, are reserved (they only convey control information). any raw pixel of value 0, 1, 2 and 3 will be substituted with 4. 2. the external pixel sequence 1023, 0 1023 is a reserved sequence (conveys control information). any raw pixel sequence of 1023, 0, 1023 w ill be substituted with 1023, 4, 1023. lvds output format in stand-alone mode, the packet size is 12 bits (2 frame bits and 10 payload bits); 10-bit pixels or 8-bit pixels can be selected. in 8-bit pixel mode (r0xb6[0] = 0), the packet consists of a start bit, 8-bit pixel data (with sync codes), the line valid bit, the frame valid bit and the stop bit. for 10-bit pixel mode (r0xb6[0] = 1), th e packet consists of a start bit, 10-bit pixel data, and the stop bit. in stereoscopic mode (see figure 47 on page 69 ), the packet size is 18 bits (2 frame bits and 16 payload bits). the packet consists of a start bit, the master pixel byte (with sync codes), the slave byte (with sync codes), and the stop bit.) table 9: lvds packet format in stand-alone mode (stereoscopy mode bit de-asserted) 12-bit packet use_10-bit_pixels bit de-asserted (8-bit mode) use_10-bit_pixels bit asserted (10-bit mode) bit[0] 1'b1 (start bit) 1'b1 (start bit) bit[1] pixeldata[2] pixeldata[0] bit2] pixeldata[3] pixeldata[1] bit[3] pixeldata[4] pixeldata[2] bit4] pixeldata[5] pixeldata[3] bit[5] pixeldata[6] pixeldata[4] bit[6] pixeldata[7] pixeldata[5] bit[7] pixeldata[8] pixeldata[6] bit[8] pixeldata[9] pixeldata[7] bit[9] line_valid pixeldata[8] bit[10] frame_valid pixeldata[9] bit[11] 1'b0 (stop bit) 1'b0 (stop bit) internal pixclk internal parallel data internal line_valid internal frame_valid external serial data out p 41 p 43 p 42 p 44 p 45 p 46 p 54 p 55 p 56 p 52 p 51 p 53 1023 1023 01p 41 p 42 p 46 2 1 p 44 p 43 p 45 p 51 p 52 p 56 3 p 54 p 53 p 55
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 58 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor feature description control signals line_valid and frame_valid can be reconstructed from their respec- tive preceding and succeeding flags that are always embedded within the pixel data in the form of reserved words. when lvds mode is enabled along with column binning (bin 2 or bin 4, r0x0d[3:2]), the packet size remains the same but the serial pi xel data stream repeats itself depending on whether 2x or 4x binning is set: ? for bin 2, lvds outputs double the expect ed data (pixel 0,0 is output twice in sequence, followed by pixel 0,1 twice, . . .). ? for bin 4, lvds outputs 4 times the expected data (pixel 0,0 is output 4 times in sequence followed by pixel 0,1 times 4, . . .). the receiving hardware will need to undersam ple the output stream getting data either every 2 clocks (bin 2) or every 4 (bin 4) clocks. if the sensor provides a pixel whose value is 0,1, 2, or 3 (that is, the same as a reserved word) then the outgoing serial pixel value is switched to 4. table 10: lvds packet format in stereoscopy mode (stereoscopy mode bit asserted) 18-bit packet function bit[0] 1'b1 (start bit) bit[1] mastersensorpixeldata[2] bit[2] mastersensorpixeldata[3] bit[3] mastersensorpixeldata[4] bit[4] mastersensorpixeldata[5] bit[5] mastersensorpixeldata[6] bit[6] mastersensorpixeldata[7] bit[7] mastersensorpixeldata[8] bit[8] mastersensorpixeldata[9] bit[9] slavesensorpixeldata[2] bit[10] slavesensorpixeldata[3] bit[11] slavesensorpixeldata[4] bit[12] slavesensorpixeldata[5] bit[13] slavesensorpixeldata[6] bit[14] slavesensorpixeldata[7] bit[15] slavesensorpixeldata[8] bit[16] slavesensorpixeldata[9] bit[17] 1'b0 (stop bit) table 11: reserved words in the pixel data stream pixel data reserved word flag 0 precedes frame valid assertion 1 precedes line valid assertion 2 succeeds line valid de-assertion 3 succeeds frame valid de-assertion
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 59 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor electrical specifications electrical specifications table 12: dc electrical characteristics v pwr = 3.3v 0.3v; t a = ambient = 25 c symbol definition condition minimum typical maximum unit v ih input high voltage v pwr - 0.5 C v pwr + 0.3 v v il input low voltage C0.3 C 0.8 v i in input leakage current no pull-up resistor; v in = v pwr or v gnd C15.0 C 15.0 a v oh output high voltage i oh = C4.0ma v pwr -0.7 C C v v ol output low voltage i ol = 4.0ma C C 0.3 v i oh output high current v oh = v dd - 0.7 C9.0 C C ma i ol output low current v ol = 0.7 C C 9.0 ma v aa analog power supply default settings 3.0 3.3 3.6 v i pwr a analog supply current default settings C 35.0 60.0 ma v dd digital power supply default settings 3.0 3.3 3.6 v i pwr d digital supply current default settings, c load = 10pf C 35.0 60 ma vaapix pixel array power supply default settings 3.0 3.3 3.6 v i pix pixel supply current default settings 0.5 1.4 3.0 ma v lvds lvds power supply default settings 3.0 3.3 3.6 v i lvds lvds supply current default settings 11.0 13.0 15.0 ma i pwr a standby analog standby supply current stdby = v dd 234 a i pwr d standby clock off digital standby supply current with clock off stdby = v dd , clkin = 0 mhz 1 2 4 a i pwr d standby clock on digital standby supply current with clock on stdby= v dd , clkin = 27 mhz C 1.05 C ma lvds driver dc specifications |v od | output differential voltage r load = 100 ? 1% 250 C 400 mv |dv od | change in v od between complementary output states CC50mv v os output offset voltage 1.0 1.2 1.4 mv dv os change in v os between complementary output states CC35mv i os output current when driver shorted to ground 10 12 ma i oz output current when driver is tri- state 1 10 a lvds receiver dc specifications v idth + input differential | v gpd | < 925mv C100 C 100 mv iin input current C C 20 a
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 60 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor electrical specifications note: 1. this is a stress rating only, and functional operat ion of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. the frequency range specified applies only to the parallel output mode of operation. propagation delays for pixclk and data out signals the pixel clock is inverted and delayed relative to the master clock. the relative delay from the master clock (sysclk) rising edge to both the pixel clock (pixclk) falling edge and the data output transition is typically 7n s. note that the falling edge of the pixel clock occurs at approximately the same time as the data ou tput transitions. see table 14 for data setup and hold times. table 13: absolute maximum ratings caution stresses greater than those listed may cause permanent damage to the device. symbol parameter minimum maximum unit v supply power supply voltage (all supplies) C0.3 4.5 v i supply total power supply current C 200 ma i gnd total ground current C 200 ma v in dc input voltage C0.3 v dd + 0.3 v v out dc output voltage C0.3 v dd + 0.3 v t stg 1 storage temperature C40 +125 c table 14: ac electrical characteristics v pwr = 3.3v 0.3v; t a = ambient = 25 c; output load = 10pf symbol definition condition minimum typical maximum unit sysclk input clock frequency note 1 13.0 26.6 27.0 mhz clock duty cycle 45.0 50.0 55.0 % t r input clock rise time 1 2 5 ns t f input clock fall time 1 2 5 ns t plh p sysclk to pixclk propagation delay c load = 10pf 3 7 11 ns t pd pixclk to valid d out (9:0) propagation delay c load = 10pf C2 0 2 ns t sd data setup time 14 16 C ns t hd data hold time 14 16 C ns t pflr pixclk to line_valid propagation delay c load = 10pf C2 0 2 ns t pflf pixclk to frame_valid propagation delay c load = 10pf C2 0 2 ns
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 61 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor electrical specifications propagation delays for frame_valid and line_valid signals the line_valid and frame_valid signals ch ange on the same rising master clock edge as the data output. the line_valid go es high on the same rising master clock edge as the output of the first valid pixel' s data and returns low on the same master clock rising edge as the end of the ou tput of the last valid pixel's data. as shown in the ?output data timing? on page 13, frame_valid goes high 143 pixel clocks before the first line_valid goes hi gh. it returns low 23 pixel clocks after the last line_valid goes low. figure 35: propagation delays for pixclk and data out signals figure 36: propagation delays for frame_valid and line_valid signals t pd t r t f t plh p t hd t sd sysclk pixclk d out (9:0) pixclk frame_valid line_valid t p flf t p flr pixclk frame_valid line_valid
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 62 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor electrical specifications performance specifications table 15 summarizes the specificatio n for each performance parameter. note: 1. all specifications address operation is at t a =25 c ( 3 c) and supply voltage = 3.3v. image sensor was tested without a lens. multiple images were captured and analyzed. setup: vdd = vaa = vaapix = lvdsvdd = 3.3v. testing was done with default frame timing and default register settings, with the exception of aec/agc, row noise correction, and auto black level, which were disabled. performance definitions are detailed in the following sections. test 1: sensitivity a flat-field light source (90 lux, color temp erature 4400k, broadband, w/ ir cut filter) is used as an illumination source. signals are measured in lsb on the sensor output. a series of four frames are captured and aver aged to obtain a scal ar sensitivity output code. test 2: dark signal nonuniformity (dsnu) the image sensor is held in the dark. analog gain is changed to the maximum setting of 4x. signals are measured in lsb on the sens or output. a series of four frames are captured and averaged (pixel-by-pixel) into one average frame. dsnu is calculated as the standard deviation of this average frame. test 3: photo response nonuniformity (prnu) a flat-field light source (90 lux, color temperature 4400k, broadband, with ir cut filter) is used as an illumination source. signals are measured in lsb on the sensor output. two series of four frames are captured and averaged (pixel-by-pixel) into one average frame, one series is captured under illuminated conditions, and one is captured in the dark. prnu is expressed as a percentage relating the standard deviation of the average frames difference (illuminated frame - dark frame) to the average illumination level: (eq 19) where s illumination (i) is the signal measured for the i -th pixel from the average illumi- nated frame, s dark (i) is the signal measured for the i -th pixel from the average dark frame, and n p is the total number of pixels contained in the array. table 15: performance specifications parameter unit minimum typical maximum test number sensitivity lsb 400 572 745 1 dsnu lsb n/a 2.3 7.0 2 prnu % n/a 1.3 4.0 3 dynamic range db 52.0 54.4 n/a 4 snr db 33.0 37.3 n/a 5 prnu 100 1 n p ----- - s illumination i () s dark i () ? () 2 i 1 = n p 1 n p ----- - s illumination i () () i 1 = n p ----------------- ----------------- ------------------ ------------------ ----------------- - =
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 63 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor electrical specifications test 4: dynamic range a temporal noise measurement is made with the image sensor in the dark and analog gain changed to the maximum setting of 4x. signals are measured in lsb on the sensor output. two consecutive dark frames are captured. temporal noise is calculated as the average pixel value of the difference frame: (eq 20) where s 1i is the signal measured for the i -th pixel from the first frame, s 2i is the signal measured for the i -th pixel from the second frame, and n p is the total number of pix- els contained in the array. the dynamic range is calculated according to the following formula: (eq 21) where t is the temporal noise measured in the dark at 4x gain. test 5: signal-to-noise ratio a flat-field light source (90 lux, color temperature 4400k, broadband, with ir cut filter) is used as an illumination source. signals are measured in lsb on the sensor output. two consecutive illuminated frames are captured . temporal noise is calculated as the average pixel value of the difference frame (according to the formula shown in test 4). the signal-to-noise ratio is calculated as the ratio of the average signal level to the temporal noise according to the following formula: (eq 22) where t is the temporal noise measured from the illuminated frames, s 1i is the signal measured for the i -th pixel from the first frame, and n p is the total number of pixels contained in the array. i s 1 i s 2 i ? () 2 i 1 = n p 2 n p ? ----------------- ------------------- = dynamicrange 20 4 1022 t ----------- --------- - log ? = signal to ? noise ? ratio ?20 s 1 i i 1 = n p ?? ?? ?? ?? n p ? ?? ?? ?? ?? t -------------------- ----------------- - log ? =
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 64 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor electrical specifications two-wire serial bus timing the two-wire serial bus operation requir es certain minimum master clock cycles between transitions. these are specified in the following diagrams in master clock cycles. figure 37: serial host interface start condition timing figure 38: serial host interface stop condition timing note: 1. all timing are in units of master clock cycle. figure 39: serial host interface data timing for write note: 1. s data is driven by an off-chip transmitter. figure 40: serial host interface data timing for read note: 1. s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off-chip. sclk 4 s data 4 sclk 4 s data 4 sclk 4 s data 4 sclk 5 s data
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 65 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor electrical specifications figure 41: acknowledge signal timing after an 8-bit write to the sensor figure 42: acknowledge signal timing after an 8-bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. temperature reference the mt9v032 contains a temperature reference circuit that can be used to measure rela- tive temperatures. contact your aptina field applications engineer (fae) for more infor- mation on using this circuit. sclk sensor pulls down s data pin 6 s data 3 sclk sensor tri-states s data pin (turns off pull down) 7 s data 6
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 66 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor electrical specifications figure 43: typical quantum efficiency ? color figure 44: typical quantum efficiency ? monochrome 0 5 10 15 20 25 30 35 40 350 450 550 650 750 850 950 1050 wavelength (nm) ) % ( y c n e i c i f f e m u t n a u q blue green (b) green (r) red 0 10 20 30 40 50 60 350 450 550 650 750 850 950 1050 wavelength (nm) ) % ( y c n e i c i f f e m u t n a u q
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 67 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor package dimensions package dimensions figure 45: 48-pin clcc package outline drawing note: 1. all dimensions in millimeters. 2. optical center = package center seating plane 4.4 11.43 5.215 5.715 lid material: borosilicate glass 0.55 thickness wall material: alumina ceramic substrate material: alumina ceramic 0.7 thickness 8.8 4.4 5.715 4.84 5.215 0.8 typ 1.75 0.8 typ 8.8 48 1 10.9 0.1 ctr 47x 1.0 0.2 48x r 0.15 48x 0.40 0.05 11.43 10.9 0.1 ctr lead finish: au plating, 0.50 microns minimum thickness over ni plating, 1.27 microns minimum thickness 2.3 0.2 1.7 nt oti l t k t first clear pixel optical center 1 c a b optical area optical area: maximum rotation of optical area relative to package edges: 1o maximum tilt of optical area relative to seating plane a : 50 microns maximum tilt of optical area relative to top of cover glass d : 100 microns a d 0.90 for reference only 1.400 0.125 0.35 for reference only v ctr ?0.20 a b c h ctr ?0.20 a b c image sensor die: 0.675 thickness 0.10 a 0.05 0.2 4x
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 68 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor appendix a C serial configurations appendix a C serial configurations with the lvds serial video output, the dese rializer can be up to 8 meters from the sensor. the serial link can save on the cabling cost of 14 wires (d out [9:0], line_valid, frame_valid, pixclk, gnd). instead, just th ree wires (two serial lvds, one gnd) are sufficient to carry the video signal. configuration of sensor for stand-alon e serial output with internal pll in this configuration, the internal pll ge nerates the shift-clk (x12). the lvds pins ser_dataout_p and ser_dataout_n must be connected to a deserializer (clocked at approximately the same system clock frequency). figure 46 shows how a standard off-the-sh elf deserializer (national semiconductor ds92lv1212a) can be used to retrieve the standard parallel video signals of d out (9:0), line_valid and frame_valid. figure 46: stand-alone topology typical configuration of the sensor: 1. power up sensor. 2. enable lvds driver (set r0xb3[4]= 0). 3. de-assert lvds power-down (set r0xb1[1] = 0. 4. issue a soft reset (set r0x0c[0] = 1 followed by r0x0c[0] = 0. if necessary: 5. force sync patterns for the deserializer to lock (set r0xb5[0] = 1). 6. stop applying sync patte rns (set r0xb5[0] = 0). sensor lvds bypass_clkin lvds ser_datain lvds shift_clkout ds92lv1212a 82 line_valid frame_valid pixel lvds ser_dataout 26.6 mhz osc. clk 26.6 mhz osc. 8 meters (maximum) 8-bit configuration shown
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 69 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor appendix a C serial configurations configuration of sensor for stereoscop ic serial output with internal pll in this configuration the internal pll gener ates the shift-clk (x18) in phase with the system-clock. the lvds pins ser_dataout_p and ser_dataout_n must be connected to a deserializer (clocked at appr oximately the same system clock frequency). figure 47 shows how a standard off-the-shelf de serializer can be used to retrieve back d out (9:2) for both the master and slave sensors. additional logic is required to extract out line_valid and frame_valid embedded within the pixel data stream. figure 47: stereoscopic topology typical configuration of the master and slave sensors: 1. power up the sensors. 2. broadcast write to de-assert lvds power-down (set r0xb1[1] = 0). 3. individual write to master sensor putting its internal pll into bypass mode (set r0xb1[0] = 1). 4. broadcast write to both sensors to set the stereoscopy bit (set r0x07[5] = 1). 5. make sure all resolution, vertical blanki ng, horizontal blanking, window size, and aec/agc configurations are done through broadcast write to maintain lockstep. 6. broadcast write to enable lvds driver (set r0xb3[4] = 0). 7. broadcast write to enable lvds receiver (set r0xb2[4] = 0). 8. individual write to master sensor, putting its internal pll into bypass mode (set r0xb1[0] = 1). 9. individual write to slave sensor, enabli ng its internal pll (set r0xb1[0] = 0). 10. individual write to slave sensor, setting it as a stereo slave (set r0x07[6] = 1). 11. individual writes to mast er sensor to minimize th e inter-sensor skew (set r0xb2[2:0], r0xb3[2:0], and r0xb4[1:0] appropriately). use r0xb7 and r0xb8 to get lockstep feedback from stereo_error_flag. 12. broadcast write to issue a soft reset (set r0x0c[0] = 1 followed by r0x0c[0] = 0). x18/x12 pll sensor sensor ds92lv16 8 8 pixel pixel from from slave master sen sor slave master 1. pll in non-bypass mode 1. pll in bypass mode 2. pll in x 18 mode (stereoscopy) lv and fv are embedded in the data stream 26.6 mhz osc. lvds ser_datain lvds bypass_clkin lvds ser_datain lvds bypass_clkin lvds shift_clkout lvds ser_dataout 5 meters (maximum) 26.6 mhz osc. lvds ser_dataout lvds shift_clkout
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 70 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor appendix a C serial configurations note: the stereo_error_flag is set if a mismatch has occurred at a reserved byte (slave and master sensor?s codes at this reserved byte must match). if the flag is set, steps 11 and 12 are repeated until the stereo_error_flag remains cleared. broadcast and individual writes for stereoscopic topology in stereoscopic mode, the two sensors are required to run in lockstep. this implies that control logic in each sensor is in exactly the same state as its pair on every clock. to ensure this, all inputs that affect control lo gic must be identical and arrive at the same time at each sensor. these inputs include: ? system clock ? system reset ? two-wire serial interface clk - scl ? two-wire serial interface data - sda figure 48: two-wire serial interface configuration in stereoscopic mode the setup in figure 48 shows how the two se nsors can maintain lockstep when their configuration registers are written through th e two-wire serial interface. a write to configuration registers would either be broadcast (simultaneous writes to both sensors) or individual (write to just one sensor at a time). reads from configuration registers would be individual (reads from just one sensor at a time). one of the two serial interface slave address bi ts of the sensor is hardwired. the other is controlled by the host. this allows the host to perform either a broadcast or a one-to- one access. broadcast writes are performed by setting the same s_ctrl_adr input bit for both slave and master sensor. individual writ es are performed by setting opposite s_ctrl_adr input bit for both slave and mast er sensor. similarly, individual reads are performed by setting opposite s_ctrl_adr input bit for both slave and master sensor. slave sensor master sensor all system clock lengths (l) must be equal. scl and sda lengths to each sensor (from the host) must also be equal. host launches scl and sda on positive edge of sysclk. scl sda host 26.6 mhz osc. l l l clk s_ctrl_adr[0] clk s_ctrl_adr[0] clk scl scl sda sda
mt9v032: 1/3-inch wide-vga digital image sensor appendix b C power-on reset and standby timing pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 71 ?2005 aptina imaging corporation all rights reserved. appendix b C power-on reset and standby timing reset, clocks, and standby there are no constraints concerning the or der in which the various power supplies are applied; however, the mt9v032 requires reset in order operate properly at power-up. refer to figure 49 for the power-up, reset, and standby sequences. figure 49: power-up, reset, clock and standby sequence note: 1. all output signals are defined during initial power-up with reset# held low without sysclk being active. to properly reset the rest of the sensor, during initial power-up, assert reset# (set to low state) for at least 750ns after all power supplies have stab ilized and sysclk is active (being clocked). driving reset# to low state does not put the part in a low power state. 2. before using two-wire serial interface, wait for 10 sysclk rising edges after reset# is de-asserted. 3. once the sensor detects that standby has been asserted, it completes the current frame readout before entering standby mode. the user must supply enough sysclks to allow a complete frame readout. see table 4, frame time, on page 13 for more information. 4. in standby, all video data and synchronization output signals are high-z. 5. in standby, the two-wire serial interface is not active. sysclk two-wire serial i/f sclk , s data reset # v dd , v dd lvds, v aa , vaapix data output standby min 10 sysclk cycles pre-standby standby wake up active driven = 0 low-power non-low-power does not respond to serial interface when standby = 1 d out [9:0] power up non-low-power min 20 sysclk cycles min 10 sysclk cycles active power down d out [9:0] note 3 min 10 sysclk cycles
pdf: 6538045704/source:2194051501 mt9v022_ds - rev. d 5/11 en 72 ?2005 aptina imaging corporation. all rights reserved. mt9v032: 1/3-inch wide-vga digital image sensor appendix b C power-on reset and standby timing standby assertion restrictions standby cannot be asserted at any time. if standby is asserted during a specific window within the vertical blanking pe riod, the mt9v032 may enter a permanent standby state. this window (t hat is, dead zone) occurs prior to the beginning of the new frame readout. the permanent standby stat e is identified by the absence of the frame_valid signal on frame readouts. issuing a hardware reset (reset# set to low state) will return the image sens or to default startup conditions. this dead zone can be avoided by: 1. asserting standby during the valid fram e readout time (frame_valid is high) and maintaining standby assertion for a minimum of one frame period. 2. asserting standby at the end of valid fr ame readout (falling edge of frame_valid) and maintaining standby assertion for a minimum of [5 + r0x06] row-times. when standby is asserted during the vertical blanking period (frame_valid is low ), the standby signal must not change state be tween [vertical blanking register (r0x06) - 5] row-times and [vertical blanking register + 5] row-times after the falling edge of frame_valid. figure 50: standby restricted location frame _valid dead zone 10 row-times vertical blanking period (r0x06) row-times 5 row-times 5 row-times
10 eunos road 8 13-40, singapore post center, singapore 408600 prodmktg@aptina.com www.aptina.com aptina, aptina imaging, and the aptina logo are the property of aptina imaging corporation all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. mt9v032: 1/3-inch wide-vga digital image sensor revision history pdf: 6538045704/source:2194051501 . mt9v022_ds - rev. d 5/11 en 73 ?2005 aptina imaging corporation all rights reserved. revision history rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/9/11 ? updated trademarks ? applied updated template rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/10 ? updated to aptina template rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/07 ? changed text in ?automatic bl ack level calibration? on page 11 ? changed ?writing (or reading) the leas t significant 8 bits to r0x80 (128)? on page 15 to ?writing (or reading) the leas t significant 8 bits to r0xf0 (240)? ? changed ?the special register addre ss (r0xf1)? on page 18 to ?the special register address (r0xf0)? ? changed wording in table 7 on page 20 row 0x00, on page 23 row 0xff, and in table 8 on page 24 row 0x00/0xff from ?rev1,? and so on to ?iter1?, and so on. ? updated legal values for r0x08, r0x09, r0x0b in table 8 on page 24 ? updated figure 24: ?latency of analog gain change when agc is disabled,? on page 46 ? changed signal name in table 13 on page 60 in maximum column, v in and v out rows, from v dd q to v dd ? moved ?propagation delays for pixclk and data out signals? up to follow table 14 on page 60 ? added section on ?performance specifications? on page 62 ? updated figure 45 ?48-pin clcc package outline drawing? on page 67 ? updated figure 46: ?stand-alone topology,? on page 68 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .06/06 ?initial release

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